(a) The same NiSi silicide is maintained on the gate and source–drain contact regions as MOSFETs are scaled according to the constant field scaling rules from the 65nm node to the 45nm node. What happens to the sheet resistance of the gate poly? Does it increase, decrease, or remain constant?

Question

(a) The same NiSi silicide is maintained on the gate and source-drain contact regions as MOSFETs are scaled according to the constant field scaling rules from the [latex]65 \mathrm{~nm}[/latex] node to the [latex]45 \mathrm{~nm}[/latex] node. What happens to the sheet resistance of the gate poly? Does it increase, decrease, or remain constant?

(b) Derive the constant field scaling rules for the peak [latex]f_{T}[/latex] value and for the optimum noise resistance [latex]R_{S O P T}[/latex] of a MOSFET, knowing that the [latex]g_{m} / W[/latex] at peak [latex]f_{T}[/latex] increases with the scaling factor S. Ignore the contribution of the source and drain resistances to [latex]f_{T}[/latex] and [latex]R_{S O P T}[/latex].

Accepted Answer

(a) The gate sheet resistance [latex]R_{S H G}= ho / t_{ ext {poly }}[/latex]
Since [latex] ho=1 /\left(q \mu_{n} N ight)[/latex] remains constant (cannot increase doping N in the silicided poly anymore) and the poly thickness decreases by S, the gate sheet resistance will increase by S. That is one of the reasons why metal gates have been introduced in high-performance (HP) [latex]45 \mathrm{~nm}[/latex] and [latex]32 \mathrm{~nm}[/latex] CMOS processes.

(b) [latex] f_{T}=\frac{g_{m}}{2 \pi\left(C_{g s}+C_{g d} ight)}=\frac{g_{m}^{\prime} W}{2 \pi\left(C_{g s}^{\prime}+C_{g d}^{\prime} ight) W} ightarrow \frac{g_{m}^{\prime}(W / S)}{2 \pi\left(C_{g s}^{\prime}+C_{g d}^{\prime} ight)(W / S)}=\frac{g_{m}^{\prime}}{2 \pi\left(C_{g s}^{\prime}+C_{g d}^{\prime} ight)}[/latex]
Since [latex]C_{g s}^{\prime}[/latex] and [latex]C_{g d}^{\prime}[/latex] do not change with scaling and [latex]g_{m}^{\prime}\left(=g_{m} / W ight)[/latex] scales by S, [latex]f_{T}[/latex] also scales by S

[latex]R_{ ext {SOPT }}=\frac{0.5}{\omega\left(C_{g s}+C_{g d} ight)}=\frac{0.5}{\omega\left(C_{g s}^{\prime}+C_{g d}^{\prime} ight) W} ightarrow \frac{0.5}{\omega\left(C_{g s}^{\prime}+C_{g d}^{\prime} ight)(W / S)}=\frac{0.5 S}{\omega\left(C_{g s}^{\prime}+C_{g d}^{\prime} ight) W} ightarrow S R_{ ext {Sopt }}[/latex]

Both [latex]f_{T}[/latex] and [latex]R_{S O P T}[/latex] scale by S. However, [latex]R_{S O P T} / W[/latex] remains constant. Since [latex]I_{D S} / W[/latex] at peak [latex]f_{T}[/latex], peak [latex]f_{M A X}[/latex] or minimum noise figure bias also remains constant with scaling, LNAs can be scaled from one technology node to another without changing the size and bias current of the transistors in the LNA, while the LNA noise figure and gain (proportional to [latex]f_{T}[/latex] ) improve.

Question 4.9: (a) The same NiSi silicide is maintained on the gate and sou...

This Question has been Answered.

Already have an account?

Login

Related Answered Questions