Calculate the emitter-to-collector transit time and the cutoff frequency of a bipolar transistor, with the following parameters.
Consider a silicon npn transistor at T=300 \mathrm{~K}. Assume the following parameters:
\begin{aligned}I_{E} &=1 \mathrm{~mA} & C_{j e} &=1 \mathrm{pF} \\x_{B} &=0.5 \mu \mathrm{m} & D_{n} &=25 \mathrm{~cm}^{2} / \mathrm{s} \\x_{d c} &=2.4 \mu \mathrm{m} & r_{c} &=20 \Omega \\C_{\mu} &=0.1 \mathrm{pF} & C_{s} &=0.1 \mathrm{pF}\end{aligned}
We will initially calculate the various time-delay factors. If we neglect the parasitic capacitance, the emitter-base junction charging time is
\tau_{e}=r_{e}^{\prime} C_{j e}
where
r_{e}^{\prime}=\frac{k T}{e} \cdot \frac{1}{I_{E}}=\frac{0.0259}{1 \times 10^{-3}}=25.9 \Omega
Then
\tau_{e}=(25.9)\left(10^{-12}\right)=25.9 \mathrm{ps}
The base transit time is
\tau_{b}=\frac{x_{B}^{2}}{2 D_{n}}=\frac{\left(0.5 \times 10^{-4}\right)^{2}}{2(25)}=50 \mathrm{ps}
The collector depletion region transit time is
\tau_{d}=\frac{x_{d c}}{v_{s}}=\frac{2.4 \times 10^{-4}}{10^{7}}=24 \mathrm{ps}
The collector capacitance charging time is
\tau_{c}=r_{c}\left(C_{\mu}+C_{s}\right)=(20)\left(0.2 \times 10^{-12}\right)=4 \mathrm{ps}
The total emitter-to-collector time delay is then
\tau_{e c}=25.9+50+24+4=103.9 \mathrm{ps}
so that the cutoff frequency is calculated as
f_{T}=\frac{1}{2 \pi \tau_{e c}}=\frac{1}{2 \pi\left(103.9 \times 10^{-12}\right)}=1.53 \mathrm{GHz}
If we assume a low-frequency common-emitter current gain of \beta=100, then the beta cutoff frequency is
f_{\beta}=\frac{f_{T}}{\beta_{0}}=\frac{1.53 \times 10^{9}}{100}=15.3 \mathrm{MHz}
Comment
The design of high-frequency transistors requires small device geometries in order to reduce capacitances, and narrow base widths in order to reduce the base transit time.