Fixed bias can also be utilized for the enhancement-mode MOSFET, as is illustrated by the circuit of Fig. 4-25. The MOSFET is described by the drain characteristic of Fig. 4-9. Let R1=60 kΩ, R2=40 kΩ, RD=3 kΩ, RL=1 kΩ, VDD=15 V, and CC→∞. (a) Find VGSQ. (b) Graphically determine VDSQ and IDQ.
(a) Assume iG=0. Then, by (4.3),
RG=R1 + R2R1R2andVGG=R1 + R2R1VDD (4.3)
(b) The dc load line is constructed on Fig. 4-9 with vDS intercept VDD=15 V and iD intercept VDD/RL=5 mA. The Q-point quantities can be read directly from projections back to the iD and vDS axes; they are VDSQ≈11.3 V and IDQ≈1.4 mA.