Question 1.3: Consider the circuit in Figure 1‐35 with the following minim...
Consider the circuit in Figure 1‐35 with the following minimum/maximum delays:
CLK‐to‐Q for flip‐flop 1: 5ns/8ns
CLK‐to‐Q for flip‐flop 2: 7ns/9ns
XOR Gate: 4ns/6ns
AND Gate: 1ns/3ns
Setup time for flip‐flops: 5ns
Hold time for flip‐flops: 2ns
(a) What is the minimum clock period that this circuit can be safely clocked at?
(b) What is the earliest time after the rising clock edge that input A can safely change?
(c) What is the latest time before the rising clock edge that input A can safely change?
(a): Since XOR gate delay is higher than the AND gate delay, and the sec‐ ond flip‐flop’s delay is greater than that of the first flip‐flop, the path from the second flip‐flop to input of the second flip‐flop via the XOR is the longest path. This path determines the maximum clock frequency. The maximum frequency is dictated by
f_{max} = 1/(t_{flip-flop-max}+t_{XORmax}+t_{su} ) \\ =1/(9+6+5)=1/20ns=50MHz(b): The earliest time after the rising clock edge that A can safely change can be obtained from equation (1‐37)
t_{y}\geq t_{h} – t_{cxmin} (1‐37)
t_{y}=t_{h} – t_{ANDmin} =2ns-1ns=1ns(c): The latest time before the rising clock edge that A can safely change can be obtained from equation (1‐36)
t_{x}\geq t_{cxmax} + t_{su} (1-36)
t_{x} = t_{ANDmax} + t_{su} =3ns+5ns=8ns