Question 9.7: Latch-up in CMOS Use the circuit in Figure 9.35 to calculat...
Latch-up in CMOS
Use the circuit in Figure 9.35 to calculate the power-supply Current I_{DD} as a function of the current I_W in the well. the current I_X in the substrate, and the well-substrate current source I_0 at the well junction. Assume that both transistors are active, and find conditions on the transistor common base gains α that cause I_{DD} to become unbounded. Assume that any voltage changes occur slowly.
Because the voltage changes occur slowly, the capacitor C_{PS} need not be considered.
By applying Kirchhoff’s Current Law to the circuit of Figure 9.35, we have
I_{DD}=I_X+I_{PE} \\ I_{DD}=I_W+I_{NE} \\ I_W=\alpha _PI_{PE}-(1-\alpha _n)I_{NE}+I_0 \\ I_X=\alpha _nI_{NE}-(1-\alpha _P)I_{PE}+I_0
Eliminating I_{PE} and I_{NE} we can write
I_{DD}=I_X+\frac{(I_W-I_0)}{\alpha _p} +\frac{(1-\alpha _n)}{\alpha _p} \times\left[\frac{(I_X-I_0)}{\alpha _n}+\frac{(1-\alpha _P)}{\alpha _n}\times(I_{DD}-I_X) \right]
Solving this expression for I_{DD} we have
I_{DD}=\frac{I_0-\alpha _PI_X-\alpha _nI_W}{1-(\alpha _n+\alpha _P)}
From this expression we see that I_{DD} tends toward infinity (and the circuit becomes latched) when the sum ( α_n + α_p ) approaches unity. This condition on the transistor αs can be compared to the latch-up constraint expressed through Equation 9.3.4. Equation 9.3.4 was obtained by applying the small-signal equivalent circuit for bipolar transistors, and thus represents a condition on the circuit gain during the transient build up to the latched condition. In this example, steady state is considered, and the r_π resistor-divider terms are not relevant. If these terms are not considered, Equation 9.3.4 simplifies to the condition β_n × β_p = 1 , or
\left(\frac{\alpha _n}{1-\alpha _n} \right) \left(\frac{\alpha _p}{1-\alpha _p} \right) =1
which reduces to ( α_n + α_p = 1 ) as concluded above.
G_L=\beta _n\times\frac{R_X}{r_{\pi pnp}+R_X} \times\beta _p\times\frac{R_W}{r_{\pi npn}+R_W} (9.3.4)