CMOS Well-Depth Design An n-well CMOS process is designed for circuit operation at VDD = 1.5 V. The starting wafers are p-type with Na = 5 × 10^14 cm^-3 . The n-wells are to have an average dopant density Nd = 3 × 10^15 cm^-3 . The p-channel MOSFET sources and drains are to have junction depths xj

Question

CMOS Well-Depth Design

An n-well CMOS process is designed for circuit operation at [latex] V_{DD} = 1.5 [/latex] V. The starting wafers are p-type with [latex] N_a = 5 × 10^{14} cm^{-3} [/latex]. The n-wells are to have an average dopant density [latex] N_d = 3 × 10^{15} cm^{-3} [/latex]. The p-channel MOSFET sources and drains are to have junction depths [latex] x_j = 0.8 [/latex] μm and an average dopant density [latex] N_a = 10^{18} cm^{-3} [/latex]. What is the minimum n-well depth that will avoid vertical punchthrough to the substrate?

Accepted Answer

Vertical punchthrough occurs in a path through the two back-to-back pn junctions from the p-channel MOSFET source, biased at [latex] V_{DD} [/latex] (1.5 V), to the grounded substrate (see Figure 9.29).

The source to n-well junction is essentially one-sided with a built-in voltage [latex] \phi _i\approx 0.78 [/latex] V.
From Table 4.1 or Equation 4.3.1, the depletion-layer width extends into the n-well 0.58 μm. The np junction to the substrate has a built-in voltage [latex] \phi _i\approx 0.58 [/latex] V, and the total depletion width at 1.5 V bias is found from Equation 4.3.1 to be 2.51 μm. Applying Equation 4.2.6, we see that one seventh of the depletion width (0.36 μm) is in the n-well. The n-well must therefore be thick enough to accommodate the depth of the drain junction (0.8 μm), as well as the total 0.94 μm (0.58 + 0.36) depleted width to avoid vertical punchthrough from the source to the substrate. Thus, the minimum well depth is 1.74 μm. Good engineering design makes it advisable to increase this dimension in order to allow a reasonable safety factor.

[latex] x_d=x_n+x_p=\left[\frac{2\epsilon _s}{q}\left(\frac{1}{N_a}+\frac{1}{N_d} \right)(\phi _i-V_a) \right] ^{1/2} [/latex] (4.3.1)

[latex] N_ax_p=N_dx_n [/latex] (4.2.6)

An additional consideration is that when the p-channel MOSFET is in the OFF-state, its drain is essentially at ground potential. In this condition, the depletion layer from well to drain is wider than that from well to source because of the added [latex] V_{DD} [/latex] voltage drop at the drain junction. However, even if the depletion regions between drain-well and well-substrate touch one another, no high punchthrough currents flow because the drain and substrate are both at ground potential. Despite this, having depletion regions touch is not good design because it may cause remote sections of the well to become pinched off. Carrying out an analysis similar to that above shows that a well depth of 2.16 μm is needed to assure that there are charge-neutral regions throughout the well under all bias conditions. With some added margin for safety, a reasonable design might make the well 2.5 μm deep.

Question 9.5: CMOS Well-Depth Design An n-well CMOS process is designed f...

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