Device Electronics for Integrated Circuits 3rd. Edition by Richard S. Muller, Theodore I. Kamins, Mansun Chan | 9780471428770 | 0471428779

Electronic Devices and Circuits

Device Electronics for Integrated Circuits

42 SOLVED PROBLEMS

Question: 10.3

MOSFET Time-to-Failure For a MOSFET with the parameters given below, calculate the time-to-failure τ for operation at VDD = 5 V. If the device is to be used in a system that must operate reliably for 10 years, what is the maximum drain-supply voltage that can be used? Device parameters are xox = ...

Verified Answer:

Using Equation 10.1.16,

\ell =0.22x_j^{1/2...

Question: 10.2

MOSFET Degradation Time In a short-channel MOSFET with xox = 30 nm, a gate current of 1 nA is momentarily caused by hot-electron injection. This gate current is estimated to flow through a section of oxide measuring 200 nm × 10 μm near the drain end of the channel. Assume that a fraction equal to ...

Verified Answer:

The gate current of 1 nA is carried by a current d...

Question: 9.6

Parameter Extraction To extract the threshold voltage and mobility of the n-channel MOSFETs obtained from a foundry, test devices are measured by applying two different gate voltages with the drain voltage kept at 0.05 V. The measured drain currents are shown in the following table. VG = 1 V VG=2 ...

Verified Answer:

At very small drain voltages

V_D

...

Question: 9.7

Latch-up in CMOS Use the circuit in Figure 9.35 to calculate the power-supply Current IDD as a function of the current IW in the well. the current IX in the substrate, and the well-substrate current source I0 at the well junction. Assume that both transistors are active, and find conditions on the ...

Verified Answer:

Because the voltage changes occur slowly, the capa...

Question: 9.4

Short-Channel Model Use the short-channel model to find values for VDsat and IDsat for a MOSFET with the following parameters: xox = 20 nm, W = 50 μm, L = 0.5 μm, VT = 0.7 V when its source is at zero potential, and with bias voltages VG = 3 V and VD = 1.5 V . Compare these results to the ...

Verified Answer:

From Equation 9.2.3 with

V_Z = 0.5 V [/lat...

Question: 10.4

Flash EPROM Programming Current An n-channel FLASH EPROM cell is programmed by hot-carrier gate current. The device parameters are VT = 0.7 V, xj = 0.2 μm, W = 100 μm, L = 0.5 μm , and (VFB + 2|Φp|) = -0.2 V. For simplicity, treat the device as a MOSFET with an extra capacitor in series with the ...

Verified Answer:

From Equation 10.5.1,

V_T

measure...

Question: 10.1

Maximum Electric Field Sketch the maximum lateral field ξm as a function of VD. ...

Verified Answer:

ξ_m

has different functional form...

Question: 9.5

CMOS Well-Depth Design An n-well CMOS process is designed for circuit operation at VDD = 1.5 V. The starting wafers are p-type with Na = 5 × 10^14 cm^-3 . The n-wells are to have an average dopant density Nd = 3 × 10^15 cm^-3 . The p-channel MOSFET sources and drains are to have junction depths xj ...

Verified Answer:

Vertical punchthrough occurs in a path through the...

Question: 9.3

Charge Sharing Consider the idealized cross section of a short-channel transistor shown in the accompanying figure. The maximum depletion width away from the source and drain junctions is xdmax, rj is the junction radius, and r2 is the radial distance to the corner of the trapezoid shown in the ...

Verified Answer:

For small values of

V_{DS}

, we co...

Question: 9.2

Subthreshold Current An n-channel MOSFET process is to be built in a p-type region doped with 8 × 10^16 cm^-3 , acceptors using an n^+ polysilicon gate. The oxide thickness is 15 nm, and the gate length is 0.8 μm. What is the ratio of the leakage currcnt that flows at VG = VT to that at VG = 0? ...

Verified Answer:

For an

n^+

polysilicon gate, n-ch...