Question 4.8: Objective: Design a source-follower amplifier with a p-chann...
Objective: Design a source-follower amplifier with a p-channel enhancement-mode MOSFET to meet a set of specifications.
Specifications: The circuit to be designed has the configuration shown in Fig-ure 4.28 with circuit parameters V_{D D} = 20 V and R_{Si} = 4 kΩ. The Q-point values are to be in the center of the load line with I_{D Q} = 2.5 mA. The input resistance is to be R_{i} = 200 kΩ. The transistor W/L ratio is to be designed such that the small signal voltage gain is A_{v} = 0.90.
Choices: A transistor with nominal parameters V_{T P} = −2 V, k´_{p} = 40 μA/V^{2} , and λ = 0 is available
(dc analysis): From a KVL equation around the source-to-drain loop, we have
V_{D D} = V_{S D Q} + I_{D Q} R_{S}
or
20 = 10 + (2.5)R_{S}
which yields the required source resistor to be R_{S} = 4 k\Omega.
(ac design): The small-signal voltage gain of this circuit is the same as that of a source follower with an NMOS device. From Equation (4.33(a)), we have
A_{v} = \frac{V_{o}}{V_{i}} = \frac{g_{m} R_{S}}{1 + g_{m} R_{S}} \cdot \frac{R_{i}}{R_{i} + R_{Si}}
which yields
0.90 = \frac{g_{m} (4)}{1 + g_{m} (4)} \cdot \frac{200}{200 + 4}
We find that the required transconductance must be g_{m} = 2.80 mA/V. The transcon-ductance can be written as
g_{m} = 2 \sqrt{K_{p} I_{D Q}}
We have
2.80 × 10^{−3} = 2 \sqrt{K_{p}(2.5 × 10^{−3})}
which yields
K_{p} = 0.784 × 10^{−3} A/V^{2}
The conduction parameter, as a function of width-to-length ratio, is
K_{p} = 0.784 × 10^{−3} = \frac{k´_{p}}{2} \cdot \frac{W}{L} = \left( \frac{40 × 10{−6}}{2} \right) \cdot \left( \frac{W}{L} \right)
which means that the required width-to-length ratio must be
\frac{W}{L} = 39.2
(dc design): Completing the dc analysis and design, we have
I_{D Q} = K_{p}(V_{G S Q} + V_{T P})^{2}
or
2.5 = 0.784(V_{SG Q} − 2)^{2}
which yields a quiescent source-to-gate voltage of V_{SG Q} = 3.79 V. The quiescent source-to-gate voltage can also be written as
V_{SG Q} = (V_{D D} − I_{D Q} R_{S}) − \left( \frac{R_{2}}{R_{1} + R_{2}} \right) (V_{D D})
Since
\left( \frac{R_{2}}{R_{1} + R_{2}} \right) = \left( \frac{1}{R_{1}} \right) \left( \frac{R_{1} R_{2}}{R_{1} + R_{2}} \right) = \left( \frac{1}{R_{1}} \right) \cdot R_{i}
we have
3.79 = [20 − (2.5)(4)] − \left( \frac{1}{R_{1}} \right) (200)(20)
The bias resistor R_{1} is then found to be
R_{1} = 644 k \Omega
Since R_{i} = R_{1}||R_{2} = 200 k\Omega, we find
R_{2} = 290 k\Omega
Comment: In order to achieve the desired specifications, a relatively large transcon-ductance is required, which means that a relatively large transistor is needed. A large value of input resistance R_{i} has minimized the effect of loading due to the output resistance, R_{Si}, of the signal source