Question 10.23: KNOWN: Thickness and thermal conductivity of a silicon chip.......
KNOWN: Thickness and thermal conductivity of a silicon chip. Properties of saturated fluorocarbon liquid.
FIND: (a) Temperature at bottom surface of chip for a prescribed heat flux and 90% of CHF, (b) Effect of heat flux on chip surface temperatures; maximum allowable heat flux.
ASSUMPTIONS: (1) Steady-state conditions, (2) Uniform heat flux and adiabatic sides, hence one-dimensional conduction in chip, (3) Constant properties, (4) Nucleate boiling in liquid.
PROPERTIES: Saturated fluorocarbon (given): \mathrm c_{\mathrm p,\ell} = 1100 J/kg·K, \mathrm h_{\mathrm{fg}} = 84,400 J/kg, ρ_{\ell} = 1619.2 kg/m³, ρ_{\mathrm v} = 13.4 kg/m³, σ = 8.1 × 10^{-3} kg/s², μ_{\ell} = 440 × 10^{-6} kg/m·s, \mathrm{Pr}_{\ell} = 9.01.
SCHEMATIC:
ANALYSIS: (a) Energy balances at the top and bottom surfaces yield \mathrm q_{\mathrm o}^{\prime\prime} = \mathrm q_{\text{cond}}^{\prime\prime} = \mathrm k_{\mathrm s} (\mathrm T_{\mathrm o} – \mathrm T_{\mathrm s})/\mathrm L = \mathrm q_{\mathrm s}^{\prime\prime}; where \mathrm T_{\mathrm s}~\text{and}~\mathrm q_{\mathrm s}^{\prime\prime} are related by the Rohsenow correlation,
T_s – T_{\text{sat}} = \frac{C_{s,f}h_{fg}Pr_{\ell}^n}{c_{p,\ell}} \left\lgroup \frac{q_s^{\prime\prime}}{\mu_{\ell}h_{fg}}\right\rgroup^{1/3} \left[\frac{\sigma}{ g \left(\rho_{\ell}~-~\rho_{ v }\right)}\right]^{1 / 6}
Hence, for \mathrm q_{\mathrm s}^{\prime\prime} = 5 \times 10^{4} W/m²,
T _{ s } – T _{\text {sat }}=\frac{0.005(84,400 J / kg ) 9.01^{1.7}}{1100 J / kg \cdot K }\left\lgroup\frac{5~ \times~ 10^4 W / m ^2}{440 ~\times ~10^{-6} kg / m \cdot s ~\times ~84,400 J / kg }\right\rgroup^{1 / 3} \times\left[\frac{8.1 ~\times ~10^{-3} kg / s ^2}{9.807 m / s ^2(1619.2~ – ~ 13.4) kg / m ^3}\right]^{1 / 6}=15.9^{\circ} C
T_s = (15.9 + 57)^{\circ}C = 72.9^{\circ}C.
From the rate equation,
T _{ o }= T _{ s }+\frac{ q _{ o }^{\prime \prime} L }{ k _{ s }}=72.9^{\circ} C +\frac{5~ \times~ 10^4 W / m ^2~ \times ~0.0025 m }{135 W / m \cdot K }=73.8^{\circ}C
For a heat flux which is 90% of the critical heat flux (\mathrm C_1 = 0.9), it follows that
q _{ o }^{\prime \prime}=0.9 q _{\max }^{\prime \prime}=0.9 \times 0.149 h _{ fg } \rho_{ v }\left[\frac{\sigma g \left(\rho_{\ell} ~- ~\rho_{ v }\right)}{\rho_{ v }^2}\right]^{1 / 4}=0.9 \times 0.149 \times 84,400 J / kg \times 13.4 kg / m ^3 \times\left[\frac{8.1~ \times ~10^{-3} kg / s ^2 ~\times ~9.807 m / s ^2(1619.2~ – ~ 13.4) kg / m ^3}{\left(13.4 kg / m ^3\right)^2}\right]^{1 / 4}
q _{ o }^{\prime \prime}=0.9 \times 15.5 \times 10^4 W / m ^2=13.9 \times 10^4 W / m ^2
From the results of the previous calculation and the Rohsenow correlation, it follows that
\Delta T _{ e }=15.9^{\circ} C \left( q _{ o }^{\prime \prime} / 5 \times 10^4 W / m ^2\right)^{1 / 3}=15.9^{\circ} C (13.9 / 5)^{1 / 3}=22.4^{\circ} C
Hence, \mathrm T_{\mathrm s} = 79.4°C and
T _{ o }=79.4^{\circ} C +\frac{13.9 ~\times ~10^4 W / m ^2~ \times ~0.0025 m }{135 W / m \cdot K }=82^{\circ} C
(b) Using the energy balance equations with the Correlations Toolpad of IHT to perform the parametric calculations for 0.2 ≤ \mathrm C_1 ≤ 0.9, the following results are obtained.
The chip surface temperatures, as well as the difference between temperatures, increase with increasing heat flux. The maximum chip temperature is associated with the bottom surface, and \mathrm T_{\mathrm o} = 80°C corresponds to
q _{o,\max}^{\prime \prime}=11.3 \times 10^4 W / m ^2
which is 73% of CHF (\mathrm q_{\max}^{\prime\prime} = 15.5 \times 10^4 W/m²).
COMMENTS: Many of today’s VLSI chip designs involve heat fluxes well in excess of 15 W/cm², in which case pool boiling in a fluorocarbon would not be an appropriate means of heat dissipation.
