A differential amplifier is designed for a typical 0.18 μm CMOS technology with L1 = L11 = 0.18 μm, L2 = L12 = 0.18 μm, W1= W11 = 18 μm and W2 = W12 = 18 μm. The lengths of the drain areas are 0.5 μm. The tail current source of IT = 400 μA is assumed ideal. The key device model parameters are

Question

A differential amplifier is designed for a typical 0.18 μm CMOS technology with [latex]L_1 = L_{11} = 0.18 \mu m[/latex], [latex]L_2 = L_{12} = 0.18 \mu m[/latex], [latex]W_1= W_{11} = 18 \mu m[/latex] and [latex]W_2 = W_{12} = 18 \mu m[/latex].

The lengths of the drain areas are 0.5 μm.

The tail current source of [latex]I_T = 400 \mu A[/latex] is assumed ideal.

The key device model parameters are listed as:
[latex]T_{ox} = 4.2 nm (C_{ox}= 8.2 imes 10^{-7} F/cm^2)[/latex],[latex] V_{ToP} =-0.43 V[/latex], [latex]\mu_{Po} = 71.2 cm^2/V.s[/latex], [latex]V_{ToN} = 0.315 V[/latex], [latex]\mu_{No} = 326 cm^2/V.s[/latex], [latex]C_{GDO} = C_{GSO} = 1.58 imes 10^{-12} F/m[/latex], [latex]C_{joP}= 1.14 imes 10^{-8} F/cm^2[/latex], [latex]C_{swP}= 1.74 imes 10^{-10} F/cm[/latex], [latex]C_{joN} =1.19 imes 10^{-8} F/cm^2[/latex], [latex]C_{sw} = 1.6 imes 10^{-10} F/cm[/latex].

Accepted Answer

The sum of the junction capacitances of M11 and M12 for zero bias can be calculated as [latex]C_{jdT} =33 fF[/latex].

Under a bias of approximately 1 V, the capacitance value is [latex]C_{jdT} = 23 fF[/latex]. The output conductances are given as [latex]g_{o11}= 91.5 \mu S[/latex] and [latex]g_{o12} = 41.25 \mu S[/latex].
The dominant pole frequency with no external load can be calculated as:

[latex]f_{L(max)}=\frac{1}{2\pi}\frac{g_o}{C_o}=\frac{1}{2\pi}\frac{(g_{o11}+g_{o12})}{C_{jdT}}[/latex]

[latex]f_{L(max)}=\frac{1}{2\pi}\frac{(91.5+41.25) imes 10^{-6}}{23 imes 10^{-15}}=918.6 MHz[/latex]

It is obvious that the external load strongly affects the bandwidth. For an external
load of only 50 fF and 1 pF, the calculated values of the pole frequencies are 289.4
MHz, and 20.6 MHz, respectively.

[latex]g_{m1}[/latex], which is necessary to find the low-frequency voltage gain, is calculated as

[latex]g_{m1}=\sqrt{2I_{D}\mu_n C_{ox}(W_1/L_1)}=\sqrt{2 imes (2 imes 10^{-4}) imes 245 imes 8.3 imes 10^{-7} imes 100}=2.85 mS[/latex]

where [latex]\mu_n= 245 cm^2/V.s[/latex] corresponds to a 0.5 V gate overdrive as a reasonable value (see Appendix A).
Now, [latex]A_{vo}[/latex] can be calculated as:

[latex]A_{vo}=\frac{g_{m1}}{g_L}=\frac{2.85 imes 10^{-3}}{132.75 imes 10^{-6}}=21.5 (26.6 dB)[/latex]

These results lead to the following observations about the circuit. The bandwidth is
primarily determined by the dominant pole related to the output node, which depends
on the sum of the output conductances of M11 and M12, the sum of the junction
capacitances of the drain regions of M11 and M12 (both being geometry-dependent)
and the load capacitance. The low-frequency gain also depends on the device geometries. Therefore, it is reasonable to investigate the effects of the input and load
transistor geometries on the gain–bandwidth product

Question 3.4: A differential amplifier is designed for a typical 0.18 μm C...

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