Question 4.DA.10: A TWO-STAGE AMPLIFIER Objective: Design a two-stage MOSFET c...
A TWO-STAGE AMPLIFIER
Objective: Design a two-stage MOSFET circuit to amplify the output of a sensor. Specifications: Assume the resistance R_{2} in the voltage divider circuit in Figure 4.60 varies linearly as a function of temperature, pressure, or some other variable. The output of the amplifier is to be zero volts when δ = 0.
Design Approach: The amplifier configuration to be designed is shown in Figure 4.60. A resistor R_{1} will be chosen such that the voltage divider between R_{1} and R_{2} will produce a dc voltage v_{I} that is negative. A negative gate voltage to M_{1} then means that the resistance R_{S1} does not need to be so large.
Choices: Assume NMOS and PMOS transistors are available with parameters
V_{T N} = 1 V, V_{T P} = −1 V, K_{n} = K_{p} = 2 mA/V^{2}, and λ_{n} = λ_{p} ≅ 0.
(voltage divider analysis): The voltage v_{I} can be written as
v_{I} = \left[ \frac{R(1 + δ)}{R(1 + δ) + 3 R} \right] (10) – 5 = \frac{(1 + δ)(10)} {4 + δ} – 5
or
v_{I} = \frac{(1 + δ)(10) – 5(4 + δ)}{4 + δ} = \frac{- 10 + 5 δ}{4 + δ}
Assuming that δ « 4, we then have
v_{I} = – 2.5 + 1.25 δ
(DC Design): We will chooseI_{D1} = 0.5 mA and I_{D2} = 1 mA The gateto-source voltages are determined to be:
0.5 = 2(V_{GS1} – 1)^{2} ⇒ V_{GS1} = 1.5 Vand
1 = 2(V_{GS2} – 1)^{2} ⇒ V_{GS2} = 1.707 VWe find V_{S1} = V_{I} – V_{GS1} = – 2.5 – 1.5 = – 4 V The resistor R_{S1} is then
R_{S1} = \frac{V_{S1} – V^{-}}{I_{D1}} = \frac{- 4 – (- 5)}{0.5} = 2 k \OmegaLetting V_{D1} = 1.5 V , we find the resistor R_{D1} to be
R_{D1} = \frac{ V^{+} – V_{D1} }{I_{D1}} = \frac{5 – 1.5}{0.5} = 7 k \OmegaWe have V_{S2} = V_{D1} + V_{SG2} = 1.5 + 1.707 = 3.207 V Then
R_{S2} = \frac{ V^{+} – V_{S2} }{I_{D2}} = \frac{5 – 3.207}{1} = 1.79 k \OmegaFor V_{O} = 0 we find
R_{D2} = \frac{V_{O} – V^{-}}{I_{D2}} = \frac{0 – (- 5)}{1} = 5 k \Omega(ac Analysis): The small-signal equivalent circuit is shown in Figure 4.61.
We find V_{2} = − g_{m1} V_{gs1} R_{D1} and V_{gs1} = V_{i}/(1 + g_{m1} R_{S1}). We also find V_{o} = g_{m2} V_{sg2} R_{D2} and V_{sg2} = − V_{2}/(1 + g_{m2} R_{S2}). Combining terms, we find
V_{o} = \frac{g_{m1} g_{m2} R_{D1} R_{D2}}{(1 + g_{m1}R_{S1})(1 + g_{m2} R_{S2})} Vi
The ac input signal is V_{i} = 1.25 δ, so we have
V_{o} = \frac{(1.25)g_{m1} g_{m2} R_{D1} R_{D2}}{(1 + g_{m1} R_{S1})(1 + g_{m2} R_{S2})} δ
We find that
g_{m1} = 2 \sqrt{K_{n} I_{D1}} = 2 \sqrt{(2)(0.5)} = 2 mA/Vand
g_{m2} = 2 \sqrt{K_{p} I_{D21}} = 2 \sqrt{(2)(1)} = 2.828 mA/VWe then find
V_{o} = \frac{(1.25)(2)(2.828)(7)(5)}{[1 + (2)(2)][1 + (2.828)(1.79)]} δ
or
V_{o} = 8.16 δ
Comment: Since the low-frequency input impedance to the gate of the NMOS is essentially infinite, there is no loading effect on the voltage divider circuit.
Design Pointer: As mentioned previously, by choosing the value of R_{1} to be larger than R_{2} , the dc voltage to the gate of M_{1} is negative. A negative gate voltage implies that the required value of R_{S1} is reduced and can still establish the required current.
Since the drain voltage at M_{1} is positive, then by using a PMOS transistor in the second stage, the source resistor value of R_{S2} is also reduced. Smaller source resistances generate larger voltage gains.
