Question 1.3: Consider the circuit in Figure 1‐35 with the following minim...
Consider the circuit in Figure 1‐35 with the following minimum/maximum delays:
CLK‐to‐Q for flip‐flop 1: 5ns/8ns
CLK‐to‐Q for flip‐flop 2: 7ns/9ns
XOR Gate: 4ns/6ns
AND Gate: 1ns/3ns
Setup time for flip‐flops: 5ns
Hold time for flip‐flops: 2ns
(a) What is the minimum clock period that this circuit can be safely clocked at?
(b) What is the earliest time after the rising clock edge that input A can safely change?
(c) What is the latest time before the rising clock edge that input A can safely change?
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