Question 8.6: Design a quadrature oscillator oscillating at 2 GHz. Phase n...

The technique is similar to the previous example, except that a four-stage differential ring oscillator as in Figure 8.44 is used. The circuit of Figure 8.49(b) is used as a delay cell. As in the previous example, to meet phase noise requirements, (8.107),

is used, resulting in a load capacitance of 100 fF. Since the frequency is twice that of the previous example, current is expected to be approximately double as well. This will require large transistors, which will add to the parasitic capacitance, requiring a further increase of current. As a first simulation, use transistor W/L of 12 \mu m/0.24 \mu m, double the size used in the previous example, to handle larger current. Biasing at 1 mA of current results in a phase noise of −98.8 dBc/Hz at a 1-MHz offset; however, the frequency is only 1.58 GHz. Thus, current is increased to 1.5 mA, transistor size is increased to a W/L of 16 \mu  m /0.24 \mu  m , the resulting phase noise is −98.6 dBc/Hz, and frequency is at 2.07 GHz. A phase noise summary indicates that the 1/f noise of the PMOS transistors is dominant, so these are increased in size to a W/L of 24 \mum/0.36 \mum. The resulting increase in parasitic capacitance is offset by an increase of current to 1.6 mA. The resulting performance is a frequency of 2.02 GHz and a phase noise of −99.99 dBc/Hz at a 1-MHz offset. The 1/f corner is at about 2.5 to 3 MHz, so further improvements are still possible. The output waveforms are shown in Figure 8.57.

With mismatched loads, phase errors will result. During layout, mismatch can be the result of mismatched connecting lines and lack of symmetry. After fabrication, further mismatch can occur due to process variation across the design. During simulation, the effect of mismatch can be explored by loading a stage differentially and to ground with capacitors or resistors. With a capacitive load on one stage, for example, representing a connection to additional transistors in dividers or mixers, the voltage on this stage will tend to change more slowly, following the capacitor equation  i = C\Delta v/\Delta t. So, if 2t is the rise time and 2\delta t is the change of rise time due to a change of capacitance \delta C, as shown in Figure 8.58 with i and \Delta vkept the same, the period changes from 8t to 8t + 2 \deltat, and the time between the desired outputs remains at 2t. Thus, the new phase is 2t/(8t + 2 \delta t) multiplied by 360°, or approximately 90° (1 − \delta t/4t). Thus, a 10% increase of rise and fall time in one stage will result in a 2.5% change of phase, or about 2°. Simulations were done with differential and single-ended capacitive and resistive loads with results as shown in Table 8.1. These numbers are close to the predicted numbers but all a bit lower.

Table 8.1 Effect of Device Mismatch on the Phase Error of a Quadrature Oscillator (Single-Ended Is Labeled ‘‘s-e;’’ Differential Is Labeled ‘‘diff’’)