Question 2.3: What is the hardware obtained if the following code is synth...
What is the hardware obtained if the following code is synthesized?
module reg3 (Q1,Q2,Q3,A,CLK);
input A;
input CLK;
output Q1,Q2,Q3;
reg Q1,Q2,Q3;
always @(posedge CLK)
begin
Q3 = Q2; // statement 1
Q2 = Q1; // statement 2
Q1 = A; // statement 3
end endmodule
A 3-bit shift register
Explanation: The list of statements executes from top to bottom in order. Note that the blocking operator is used. Therefore, the first statement finishes update before the second statement is executed. Synthesis results in a 3-bit shift register with serial input A, and out- puts Q_{1} , Q_{2} and Q_{3}
Note: While a register can be modeled using the blocking operator “=” as in this example, it is generally advised to not do so. As mentioned previously, a good coding practice while writing synthesizeable code is to use non-blocking assignments (i.e., “<=”) in always blocks intended to create sequential logic, and the blocking operator “=” in always blocks intended to create combinational logic.