What is the hardware obtained if the following code is synthesized? Note that this is the same code as in the previous example, but with the statement order inside the always block reversed.

Question

module reg31 (Q1,Q2,Q3,A,CLK);

input A;

input CLK;

output Q1,Q2,Q3;

reg Q1,Q2,Q3;

always @(posedge CLK)

begin

Q1 5 A; // statement 1

Q2 5 Q1; // statement 2

Q3 5 Q2; // statement 3

end  endmodule

Accepted Answer

A single flip-flop

Explanation: The list of statements executes from top to bottom in order. Note that the blocking operator is used. So the first statement finishes update before the second statement is executed. [latex]Q_{1} [/latex] gets the value of the serial input A when statement 1 finishes. In statement 2, the same value propagates to [latex]Q_{2}[/latex] . In statement 3, the same value propagates to [latex]Q_{3}[/latex] . In effect, the input A has reached [latex]Q_{3} [/latex]. Modern synthesis tools will generate a single flip-flop with input A when this code is synthesized. The outputs [latex]Q_{1} [/latex], [latex]Q_{2}[/latex] , and [latex]Q_{3}[/latex] can all be connected to the output of the same flip-flop. If the synthesizer does not have good optimization algorithms, it might generate three parallel flip-flops, each with the same input A but with outputs [latex]Q_{1} [/latex], [latex]Q_{2}[/latex] , and [latex]Q_{3}[/latex] , respectively. As mentioned in the Note to Example 2.3, it is not a good practice to use the blocking operator “=” in always blocks intended to create sequential logic. If one were to use non-blocking statements, the order of the statements would not have mattered.

Question 2.4: What is the hardware obtained if the following code is synth...

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