Question 2.3: What is the hardware obtained if the following code is synth...
What is the hardware obtained if the following code is synthesized?
module reg3 (Q1,Q2,Q3,A,CLK);
input A;
input CLK;
output Q1,Q2,Q3;
reg Q1,Q2,Q3;
always @(posedge CLK)
begin
Q3 = Q2; // statement 1
Q2 = Q1; // statement 2
Q1 = A; // statement 3
end endmodule
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