65nm CMOS chain scaling
Consider a 6-stage CMOS amplifier chain where each stage has minimum gate length transistors, with W=20 \mu \mathrm{m} and 20 unit fingers, each 1 \mu \mathrm{m} wide and contacted on both sides of the gate. R_{D}=200 \Omega. Each stage is biased at 0.15 \mathrm{~mA} / \mu \mathrm{m} and the corresponding small signal parameters of the MOSFET are R_{g}=10 \Omega,\left(200 \Omega / N_{f}\right) C_{g s}^{\prime}=0.7 \mathrm{fF} / \mu \mathrm{m}, C_{s b}^{\prime}=C_{d b}^{\prime}=0.7 \mathrm{fF} / \mu \mathrm{m}, C_{g d}^{\prime}=0.4 \mathrm{fF} / \mu \mathrm{m}, g^{\prime}{ }_{m e f f}=0.9 \mathrm{mS} / \mu \mathrm{m}, g_{\text {oeff }}^{\prime}=0.18 \mathrm{mS} / \mu \mathrm{m}. (a) Calculate the DC gain, the 3 \mathrm{~dB} bandwidth and the gain-bandwidth product of the individual stage and of the amplifier chain. (b) Re-design the amplifier chain using size and bias scaling by a factor of 2 from the input to output, knowing that the first stage has R_{D}=62.5 \Omegaand W=64 \mu \mathrm{m}. Assume the same bias current density, and small signal parameters per unit gate width as in the original amplifier.