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## Q. 5.7

65nm n-MOS common-source stage with shunt peaking For the circuit in Example 5.6, find the value of the peaking inductor and bandwidth extension if a maximally flat gain response is desired.

## Verified Solution

The load resistance $R_{D}$ is $200 \Omega$ and the total capacitance at the output node is

$C=\left[C_{d b}+C_{g s}+\left(2+\left|A_{0}\right|\right) C_{g d}\right]=14 \mathrm{fF}+14 \mathrm{fF}+32.8 \mathrm{fF}=60.8 \mathrm{fF}$

The peaking inductance value for flat gain response is obtained from (5.76)

$L_P=0.4R_C^2C_1$                        (5.76)

$L_{P}=0.4 R_{D}^{2} C=0.97 n H$

which results in a bandwidth of $1.7 \times 21.1 \mathrm{GHz}=35.87 \mathrm{GHz}$.

Computer simulation using the design kit and BSIM4 MOSFET models shows that

$A_{S}^{\prime}=6.4 \mathrm{~dB}(2.089)$, $B W_{S}^{\prime}=32.96 \mathrm{GHz}$,$A_{\text {tot }}^{\prime}=38.38 \mathrm{~dB}(83)$,$B W_{\text {tot }}^{\prime}=15.5 \mathrm{GHz}$, $G B W_{S}^{\prime}=68.85 \mathrm{GHz}$, $G B W_{t o t}^{\prime}=1.286 \mathrm{THz}$

We note that, compared to the case without peaking, the simulated bandwidth has improved by a factor of 32.96/18.96 = 1.74, very close to the theoretical value. This is a significantly larger GBW than that obtained in the case where only scaling, without inductive peaking is applied. The two amplifier chains consume approximately the same current 18mA (inductive peaking), and 19mA (scaling), respectively, from a 1.2V supply. A disadvantage of the stage with inductive peaking is that it requires a larger die area because of the area occupied by the peaking inductor. However, in a typical multi-metal CMOS back-end, the size of a 600pH inductor can be made as small as $10 \mu \mathrm{m} \times 10 \mu \mathrm{m}$.

More complicated inductive peaking schemes, with increasing number of inductors, can lead to even larger bandwidth extension:

shunt–series peaking, employing two inductors, Figure 5.31b, results in a doubling of the bandwidth compared to that of the original amplifier stage without inductive elements; shunt and double-series peaking using a t-coil as in Figure 5.32, producing a 2.8x increase in bandwidth;

distributed amplifier (DA) topology, leading to the largest possible bandwidth for a given transistor technology.

The benefits of the distributed amplifier topology, invented by Parcival in 1936 , can be explained by first considering the expression of the characteristic impedance and 3dB band- width of a transmission line with line impedance L and line capacitance C

$z_{0}=\sqrt{\frac{L}{C}} \operatorname{and} B W_{3 \mathrm{ad}}=\frac{1}{\pi \sqrt{\mathrm{CL}}}$                        (5.78)

If the original lumped amplifier stage with load resistance $R_{D}$, input capacitance $C_{I}$, and output capacitance $C_{O}$ is spit into m identical stages, each with an input capacitance $C_{I}/m$ and an

output capacitance $C_{O} / m$, the overall DC gain remains the same. If we now connect the inputs to a distributed input transmission line of inductance $L_{I}$, and the outputs to a distributed output transmission line of inductance $L_{O}$, such that

$L_{I}=Z_{0}^{2} \frac{C_{I}}{m} \text { and } L_{O}=R_{D}^{2} \frac{C_{O}}{m}$                                (5.79)

the input line will have a characteristic impedance $Z_{0}$ and must be terminated on$Z_{0}$, while the output line will have a characteristic impedance equal to $R_{D}$ and must be terminated on $R_{D}$ at both ends. The resulting distributed amplifier schematic is shown in Figure 5.33. We note that, at DC, all inductors behave as short circuits and that the voltage gain is reduced in half compared to that of the lumped stage because of the presence of the second load resistance, $R_{D}$, needed to match the output transmission line

$A=-m \frac{g_{m e f f}}{m} \frac{R_{D}}{2}=-g_{m e f f} \frac{R_{D}}{2}$                                (5.80)

The bandwidth is given by the smaller of the 3dB bandwidths of the input and output transmission lines

$B W_{3 \mathrm{~dB}}=\min \left(\frac{1}{\pi \sqrt{L_{\mathrm{I}} \frac{C_{I}}{m}}}, \frac{1}{\pi \sqrt{L_{\mathrm{O}} \frac{C_{O}}{m}}}\right)$                                (5.81)

Usually, $C_{i}=C_{O}$ (if not, extra capacitance is added in parallel with the smaller of the two) to ensure that the output and input transmission lines have identical delays and cutoff frequencies. If we set $Z_{0}=R_{D}$, then

$B W_{3 \mathrm{~dB}}=\min \left(\frac{m}{\pi R_{D} C_{\mathrm{I}}}, \frac{m}{\pi R_{D} C_{\mathrm{O}}}\right)$                                (5.82)

which, in theory, can be made infinite if $m \rightarrow \infty$.

Since the GBW of the original lumped stage is

$G B W_{S}=\frac{g_{m e f f}}{2 \pi\left(C_{\mathrm{I}}+C_{\mathrm{O}}\right)}$                                (5.83)

the gain-bandwidth product of the distributed amplifier

$G B W_{S}^{\prime}=\min \left(m \frac{g_{m e f f}}{2 \pi C_{\mathrm{I}}}, m \frac{g_{m e f f}}{2 \pi C_{\mathrm{O}}}\right)$                                (5.84)

becomes at least  $2 \times \mathrm{m}$ larger, because the node capacitance has been split in two ( $C_{I}$  and $C_{O}$ )and both  $C_{I}$ and  $C_{O}$ have been reduced m-times compared to those of the original lumped stage.

Ultimately, the GBW of the distributed amplifier is limited by the  $f_{M A X}$ of the transistor. The parasitic base/gate resistance and output resistance of the transistor, the loss of the transmission lines, all ignored in the previous analysis, contribute increasing loss to the input and output t-lines as the number of sections in the DA increases. Therefore, in practice the number of sections is between 4 and 7 .

The gain cell in the distributed amplifier can be a transistor (usually a FET due to its high- Q input impedance), a cascode stage, other more advanced amplifier stages such as EF + cascode, and even a multi-stage lumped amplifier . In each situation, the bandwidth of the distributed amplifier far exceeds that of the unit gain cell. In the case of HBT amplifiers, the gain cell usually employs an emitter-follower at its input in order to increase the input impedance and thus minimize the loss along the input transmission line. In SiGe BiCMOS technologies, the MOS-HBT cascode provides both high-Q input and output impedances, large output voltage swing, and large gain cell bandwidth .
It should be noted that, although most of these topologies have “peaking” in their name, the design is conducted in such a manner that peaking is avoided in both the amplitude and in the group delay response of the transfer characteristics. When in doubt, it is always wise to design on the side of caution, to avoid peaking in all process corners, by choosing smaller values for the peaking inductors.   