Analyze the implementing functionality of an asynchronous sequential circuit, as shown in Figure 6.2.5.

Step-by-Step

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Step 1 Derive the clock equations and exciting equations directly from the logic diagram shown in Figure 6.2.5.

The clock equations are

C P_{0}=C P\quad C P_{1}=Q_{0n}\quad C P_{2}=Q_{1n} (6.2.13)

The exciting equations for D flip-flops are

D_{0}=\bar{Q}_{0n}\quad D_{1}=\bar{Q}_{1n}\quad D_{2} =\bar{Q}_{2n} (6.2.14)

Step 2 Derive the state equation of each flip-flop by substituting the exciting equations into the characteristic equation of each flip-flop.

The characteristic equation of D flip-flops is

Q_{n+1}=D (6.2.15)

The state equations can be derived as

Q_{0n+1}=\bar{{Q}_{0}}_{n}\quad Q_{1n+1} =\bar{{Q}_{1}} _{n} \quad Q_{2n+1}=\bar{Q}_{2n} (6.2.16)

Step 3 Construct the state table from the state equations and output equation.

The possible state transition of D flip-flop occurs at the arriving of the negative edge of the clock signal. Thus, we use CP = 1 to represent the negative edge of the clock signal. For D flip-flops, the next state can be solved by eq. (6.2.15) when CP = 1. While the next state is the same as the present state when CP = 0. Assume that the initial state is Q_{2}Q_{1}Q_{0} = 000; the next state can be derived by the state equations and clock equations. When the first clock signal arrives, C P_{0} = 1 and thus the next state of FF0 can be calculated by eq. (6.2.16). Since Q_{0n} is a 0, Q_{0n+1} is a 1. Then we turn to determine the next state of FF1. Since Q_{0} is changed fromLOWto HIGH, \ C P_{1} = 0 and thus Q_{1} does not change. The next state of FF1 is a 0. When the Q_{1} keeps no change, \ C P_{2} = 0 and thus Q_{2} also keeps no change. So when the first clock signal arrives, the next state of an asynchronous sequential circuit will be Q_{2}Q_{1}Q_{0} = 001. Similarly, you can analyze the next state of an asynchronous sequential circuit when the sequential clock signal arrives. The final state table is shown in Table 6.2.4. In the state table of an asynchronous sequential circuit, the column of clock signal is added to represent if the flip-flop is clocked by negative edge of the CP. If the flip-flop is clocked, CP = 1.

Step 4 Draw a timing diagram from the state table and deduce the implementing functionality of the given sequential logic circuits.

All D flip-flops are triggered at the negative edge of their CP. According to the stable table, a timing diagram is shown in Figure 6.2.6. It can be seen from the timing diagram, the asynchronous sequential circuit in Figure 6.2.5 goes through the states in the following sequence: 000, 001, 010, 011, 100, 101, 110, 111, 000, … After eight CPs, the state of asynchronous sequential circuit goes back to 000 and then starts a new count cycle again. Therefore, the asynchronous sequential circuit shown in Figure 6.2.6 works as an asynchronous three-bit binary up counter.

Table 6.2.4: A state table. | ||||||

CP | Q_{2} | Q_{1} | Q_{0} | CP_{2} | CP_{1} | CP_{0} |

0 | 0 | 0 | 0 | 0 | 0 | 0 |

1 | 0 | 0 | 1 | 0 | 0 | 1 |

2 | 0 | 1 | 0 | 0 | 1 | 1 |

3 | 0 | 1 | 1 | 0 | 0 | 1 |

4 | 1 | 0 | 0 | 1 | 1 | 1 |

5 | 1 | 0 | 1 | 0 | 0 | 1 |

6 | 1 | 1 | 0 | 0 | 1 | 1 |

7 | 1 | 1 | 1 | 0 | 0 | 1 |

8 | 0 | 0 | 0 | 1 | 1 | 1 |

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