# Question 6.6: Design an 8421BCD asynchronous up counter with a ripple carr......

Design an 8421BCD asynchronous up counter with a ripple carry output.

Step-by-Step
The 'Blue Check Mark' means that this solution was answered by an expert.
Learn more on how do we answer questions.

Step 1 Construct the state table.
Because an 8421BCD counter has ten states represented by ten fixed binary code, the coded state table can be listed directly, as shown in Table 6.3.7. Z is defined as the ripple carry output.

Step 2 Choose the type of flip-flops to be used. Derive the excitation equations and output equation.
The 8421BCD has four-bit binary codes and thus four flip-flops are required. Here, four J-K flipflops are chosen to construct the 8421BCD asynchronous up counter.
Since there is no global clock signal for all flip-flops in asynchronous circuit, the CP for each flipflop must be applied as long as the state of flip-flop produce a change .
According to Table 6.3.7, the output $Q_1$ of the first flip-flop changes state at each CP, so the input CP as its clock input. That is, ${{C P}}_{1}={{C P}}$ and $J_{1}=K_{1}$ = 1.
The output $Q_{2}$ of the first flip-flop changes its state when  $Q_{1}$ changes from HIGH to LOW, that is, at the negative going edge of $Q_{1}$ . Thus, $Q_{1}$ is set as the input CP of the second flip-flop, $CP_{2}=Q_{1}.$

Note that at the 10th CP, although $Q_{1}$ changes from HIGH to LOW, $Q_{2}$ does not change. Thus, $J_{2}$ and $K_{2}$ input for the second flip-flop should be controlled to make sure that $Q_{2}$ does not change at the 10th CP.
The output $Q_{3}$ changes its state when $Q_{2}$ changes from HIGH to LOW, so $Q_{2}$ is set as the input CP of the third flip-flop, $C P_{3}$ = $Q_{2}$ and $J_{3}$ = $K_{3}$ = 1.
The output $Q_{4}$ changes state when $Q_{1}$ changes from HIGH to LOW, so $Q_{1}$ is set as the input CP of the fourth flip-flop, $CP_{4}=Q_{1}.$  Note that the $J_{4}$ and $K_{4}$ input still need to be controlled since $Q_{4}$ does not change at its first three CP.
According to aforementioned analysis, Table 6.3.7 can be simplified as Table 6.3.8.

The state transition table is shown as Table 6.3.9.

According to Table 6.3.9, the Karnaughmaps of the inputs of J-K flip-flops are shown in Figure 6.3.10.
Excitation equations can be obtained by Karnaugh map simplification as follows:

$\begin{cases} J_{4}=Q_{3}Q_{2} \\ K_{4}=1 \end{cases} , \quad \ \begin{cases} J_{2}=\bar{Q}_{4} \\ K_{2}=1 \end{cases}$          (6.3.6)

Only when $Q_{4}\,Q_{3}\,Q_{2}\,Q_{1}$ = 1001, Z = 1, the output equation is

${{{Z}}}=Q_{4}\,\bar{Q}_{3}\,\bar{Q_{2}}\,Q_{1}$                    (6.3.7)

Step 3 Check if the 8421BCD asynchronous up counter can be self-corrected.
There are six unused states from 1010 and 1111. Assume that the circuit is in state 1010, when next CP is applied to the clock input of FF1, the next state of the output $Q_{{1}}$ changes from a 0 to a 1 since the values of J and K inputs are both 1. With $Q_{{1}}$ from LOW to HIGH, there is no falling edge of CP applied to the clock input of FF2 and thus the output $Q_{{2}}$ still keeps a 1. Since the output of $Q_{{2}}$ does not change, there is no effective CP applied to the clock input of FF3 and thus the output $Q_{{3}}$ also keeps a 0. With $Q_{{1}}$ from LOW to HIGH, there is no falling edge of CP applied to the clock input of FF4 and thus the output $Q_{{4}}$ does not change. Thus, after state 1010, the next state is state 1011.
Assume that the circuit is in state 1011; when next CP is applied to the clock input of FF1, the next state of the output $Q_{{1}}$ changes from a 1 to a 0 since the values of J and K inputs are both 1. With $Q_{{1}}$ from HIGH to LOW, there is a falling edge of CP applied to the clock input of FF2 and FF4. Therefore, the output $Q_{{2}}$ changes from a 1 to a 0 due to $J_{{2}}$ = 0 and $K_{{2}}$ = 1 and the output $Q_{{4}}$ changes from a 1 to a 0 since $J_{{4}}$ = 0 and $K_{{4}}$ = 1. With $Q_{{2}}$ from HIGH to LOW, there is a falling edge of CP applied to the clock input of FF3 and thus the output $Q_{{3}}$ changes from a 0 to a 1 since $J_{{3}}$ = $K_{{3}}$ = 1. It is clearly seen that the next state is state 0100 after state 1011. Similarly, you can check the other four unused states. The complete state diagram is shown in Figure 6.3.11. It can be seen from Figure 6.3.11 that the design circuit can be self-corrected.

Step 3 Draw a logic diagram according to excitation equations and output equation.
According the excitation eq. (6.3.6) and output eq. (6.3.7), the logic diagram of the 8421BCD asynchronous up counter is implemented with four J-K flip-flops, as shown in Figure 6.3.12.

 Table 6.3.7: The state table. CP $Q_{4}$ $Q_{3}$ $Q_{2}$ $Q_{1}$ Z 0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 0 9 1 0 0 1 1 10 0 0 0 0 0
 Table 6.3.8: The simplified state table. CP $Q_{4}$ $Q_{3}$ $Q_{2}$ 0 0 0 0 2 0 0 1 4 0 1 0 6 0 1 1 8 1 0 0
 Table 6.3.9: The state transition table. CP Present state Next state Excitation inputs $Q_{4n}$ $Q_{3n}$ ${Q_{2n}}$ ${Q_{4n+1}}$ ${Q_{3n+1}}$ ${Q_{2n+1}}$ $J_{4}$ $K_{4}$ $J_{2}$ $K_{2}$ 0 0 0 0 0 0 1 0 × 1 × 2 0 0 1 0 1 0 0 × × 1 4 0 1 0 0 1 1 0 × 1 × 6 0 1 1 1 0 0 1 × × 1 8 1 0 0 0 0 0 × 1 0 ×

Question: 6.5

## Verified Answer:

Step 1 Construct the state diagram and state table...
Question: 6.4

## Verified Answer:

Step 1 Construct the initial state diagram and ini...
Question: 6.3

## Verified Answer:

Step 1 Derive the clock equations and exciting equ...
Question: 6.2

## Verified Answer:

Step 1 Derive the exciting equations and output eq...
Question: 6.1

## Verified Answer:

Step 1 Derive the exciting equations and output eq...
Question: 6.6

## Verified Answer:

Step 1 Construct an implication chart. The implica...