Question 6.2: Analyze the implementing functionality of an SSC, as shown i......

Analyze the implementing functionality of an SSC, as shown in Figure 6.2.3.

Step-by-Step
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Step 1 Derive the exciting equations and output equations directly from the logic diagram shown in Figure 6.2.3.
There are two J-K flip-flops in the circuit; the exciting equations are

$J_{1}=K_{1}=1$                            (6.2.7)

$J_{2}=K_{2}=Q_{1}$                        (6.2.8)

The output equation is

$Y=Q_{1}Q_{2}$                  (6.2.9)

Step 2 Derive the state equation of each flip-flop by substituting the exciting equations into the characteristic equation of each flip-flop.
The characteristic equation of J-K flip-flops is

$Q_{n+1}=J \bar{Q}_{n}+\bar{K}Q_{n}$                        (6.2.10)

Thus, the state equations can be expressed as

$Q_{1}{_{n}^{+}}=\bar{Q}_{1}$                      (6.2.11)

$Q_{2}{_{n}^{+}}=Q_{1}\bar{Q}_{2}+\bar{Q}_{1}Q_{2}=Q_{1}\oplus Q_{2}$                    (6.2.12)

Step 3 Construct a state table from the state equations and output equation.
The state table is shown as Table 6.2.3

Step 4 Draw a state diagram from the state table and deduce the implementing functionality of the given sequential logic circuits.
The state diagram is shown in Figure 6.2.4. It can be found that the sequential circuit goes through the states in the following sequence: 00, 01,10, 11,00, 01, … When it counts to 11, the output is a HIGH. When the next clock arrives, the circuit goes back to the initial state 00, and start new count cycle again. Since this sequence is characteristic of modulus-4 counting, we can conclude that the sequential circuit in Figure 6.2.3 is a modulus-4 counter and belongs to the Moore model due to no input signal.

 Table 6.2.3: A state table. Present state Next state Output $Q_{2}$ $Q_{1}$ ${Q_{2}}^{+}$ ${Q_{1}}^{+}$ Y 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1

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