Design a synchronous counter with J-K flip-flops. The timing diagram for the counter is shown as Figure 6.3.4.

Step-by-Step

Learn more on how do we answer questions.

Step 1 Construct the state diagram and state table directly from time diagram in Figure 6.3.4. Then determine the number of flip-flops.

The state diagram can be deduced by analyzing the timing diagram in Figure 6.3.4. The initial state is 000. When the falling edge of the first CP arrives, the state transition occurs from state 000 to state 001. Then the state will change from state 001 to state 100 at the falling edge of the second CP. After six CPs, the counter returns to the initial state. Figure 6.3.5 shows the state diagram of the synchronous counter. The state table can be obtained from the state diagram in Table 6.3.6. It can be seen from Table 6.3.6 that the synchronous counter has six used states and thus at least three J-K flip-flops are required.

Step 2 Derive the excitation equations.

Here, we choose another method to deduce the excitation equations of each flip-flop. First, the state equations can be derived from the state table by Karnaugh map simplification. Karnaugh maps of next state can be obtained from state table, as shown in Figure 6.3.6. Next states, Q_{2n+1}Q_{1n+1}Q_{0n+1} , are listed in the cell of Karnaugh map.

In order to obtain the minimized next state equations, the Karnaugh map in Figure 6.3.6 are divided into three Karnaugh maps, as shown in Figure 6.3.7.

By using Karnaugh map simplification in Figure 6.3.7, the minimized state equations can be deduced as follows:

Compare each state equation with the characteristic equation of J-K flip-flop, Q_{n+1}=J \bar{Q}_{n}+\bar{K} Q_{n} ; the excitation equations for each J-K flip-flop are deduced as follows:

\begin{cases} J_{2}=Q_{0n} \\ K_{2}=1 \end{cases} , \quad \begin{cases} J_{1}=Q_{2n} \\ K_{1}=1 \end{cases} , \quad \begin{cases} J_{0}=\bar{Q}_{1n} \\ K_{0}=\bar{Q}_{1n} \end{cases} (6.3.5)

Step 3 Check if the synthesis of sequential logic circuits can be self-corrected.

There are two unused states, 110 and 111. If in state 110, the next state is 000, which can be obtained by substituting the current state 110 into state eq. (6.3.4). Similarly, if in state 111, the next state is 001. The state diagram containing all states is shown in Figure 6.3.8. Since both state 000 and state 001 are the used states, the design resulting circuit can be selfcorrected.

Step 4 Draw a logic diagram according to the resulting exciting equations.

According the excitation eq. (6.3.5), the logic diagram of the synchronous counter is implemented with three J-K flip-flops, as shown in Figure 6.3.9.

Table 6.3.6: The state table. | |||||

Current state | Next state | ||||

Q_{2n} | Q_{1n} | Q_{0n} | Q_{2n+1} | Q_{1n+1} | Q_{0n+1} |

0 | 0 | 0 | 0 | 0 | 1 |

0 | 0 | 1 | 1 | 0 | 0 |

0 | 1 | 0 | 0 | 0 | 0 |

0 | 1 | 1 | 1 | 0 | 1 |

1 | 0 | 0 | 0 | 1 | 1 |

1 | 0 | 1 | 0 | 1 | 0 |

Question: 6.6

Step 1 Construct the state table.
Because an 8421B...

Question: 6.4

Step 1 Construct the initial state diagram and ini...

Question: 6.3

Step 1 Derive the clock equations and exciting equ...

Question: 6.2

Step 1 Derive the exciting equations and output eq...

Question: 6.1

Step 1 Derive the exciting equations and output eq...

Question: 6.6

Step 1 Construct an implication chart.
The implica...