Question 15.1: Consider MOS transistors fabricated in a 0.25-μm CMOS proces...
Consider MOS transistors fabricated in a 0.25-μm CMOS process for which VDD = 2.5 V, Vtn = −Vtp = 0.5 V, μnCox = 115 μA/V², μpCox = 30 μA/V², λn = 0.06 V-1, and |λp| = 0.1 V-1. Let L = 0.25 μm and (W/L)n = (W/L)p = 1.5. Measurements indicate that for the NMOS transistor, VDSsat = 0.63 V, and for the PMOS device, |VDSsat| = 1 V. Calculate the drain current obtained in each of the NMOS and PMOS transistors for |VGS| = |VDS| = VDD. Compare with the values that would have been obtained in the absence of velocity saturation. Also give the range of vDS for which iD is saturated, with and without velocity saturation.
For the NMOS transistor, VGS = 2.5 V results in VGS − Vtn = 2.5 − 0.5 = 2 V, which is greater than VDSsat. Also, VDS = 2.5 V is greater than VDSsat ; thus both conditions in Eq. (15.12) are satisfied,
vGS − Vt ≥ VDSsat and vDS ≥ VDSsat (15.12)
and the NMOS transistor will be operating in the velocity-saturation region, and thus iD is given by Eq. (15.11):
i_{D} = μ_{n}C_{ox} \left(\frac{W}{L}\right) V_{DSsat} \left(v_{GS} – V_{t} – \frac{1}{2}V_{DSsat}\right) (1 + λv_{DS}) (15.11)
i_{D} = 115 × 10^{−6} × 1.5 × 0.63 × \left(2.5 – 0.5 – \frac{1}{2} × 0.63\right) × (1 + 0.06 × 2.5) = 210.6 μA
If velocity saturation were absent, the current would be
i_{D} = \frac{1}{2} (μ_{n}C_{ox}) \left(\frac{W}{L}\right)_{n} (v_{GS} – V_{tn})^{2} (1 + λv_{DS})
= \frac{1}{2} × 115 × 10^{−6} × 1.5 × (2.5 – 0.5)^{2} × (1 + 0.06 × 2.5)
= 396.8 μA
Thus, velocity saturation reduces the current level by nearly 50%! The saturation current, however, is obtained over a larger range of vDS; specifically, for vDS = 0.63 V to 2.5 V. (Of course, the current does not remain constant over this range because of channel-length modulation.) In the absence of velocity saturation, the current saturates at VOV = VGS − Vt = 2 V, and thus the saturation current is obtained over the range vDS = 2 V to 2.5 V.
For the PMOS transistor, we see that since |VGS| − |Vt| = 2 V and |VDS| = 2.5 V are both larger than |VDSsat| = 1 V the device will be operating in velocity saturation, and iD can be obtained by adapting Eq. (15.11) as follows:
i_{D} = (μ_{p}C_{ox}) \left(\frac{W}{L}\right)_{p} |V_{DSsat}| \left(|v_{GS}| – |V_{tp}| – \frac{1}{2}|V_{DSsat}|\right) (1 + |λ_{p}||V_{DS}|)
= 30 × 10^{−6} × 1.5 × 1 × \left(2.5 – 0.5 – \frac{1}{2} × 1 \right) (1 + 0.1 × 2.5)
= 84.4 μA
Without velocity saturation, we have
i_{D} = \frac{1}{2} (μ_{p}C_{ox}) \left(\frac{W}{L}\right)_{p} (|v_{GS}| – |V_{tp}|)^{2} (1 + |λ_{p}||V_{DS}|)
= \frac{1}{2} × 30 × 10^{−6} × 1.5 × (2.5 – 0.5 )^{2} (1 + 0.1 × 2.5)
= 112.5 μA
Thus velocity saturation reduces the current by 25% (which is less than in the case of the NMOS transistor), and the saturated current is obtained over the range |VDS| = 1 V to 2.5 V. In the absence of velocity saturation, the saturated iD would have been obtained for |VDS| = 2 V to 2.5 V.