Consider the four-input, dynamic logic NAND gate shown in Fig. 15.29(a). Assume that the gate is fabricated in a 0.18-μm CMOS technology for which VDD = 1.8 V, Vt = 0.5 V, and μnCox = 4 μpCox = 300 μA/V². To keep CL small, NMOS devices with W/L = 0.27 μm/0.18 μm are used (including transistor Qe).

Question

Consider the four-input, dynamic logic NAND gate shown in Fig. 15.29(a). Assume that the gate is fabricated in a 0.18-μm CMOS technology for which V_DD = 1.8 V, V_t = 0.5 V, and μ_nC_ox = 4 μ_pC_ox = 300 μA/V². To keep C_L small, NMOS devices with W/L = 0.27 μm/0.18 μm are used (including transistor Q_e). The PMOS precharge transistor Q_p has W/L = 0.54 μm/0.18 μm. The total capacitance C_L is found to be 20 fF.

(a) Consider the precharge operation [Fig. 15.29(b)] with the gate of Q_p at 0 V, and assume that at t = 0, C_L is fully discharged. Calculate the rise time of the output voltage, defined as the time for v_Y to rise from 10% to 90% of the final voltage V_DD.

(b) For A = B = C = D = 1, find the value of t_PHL.

Accepted Answer

(a) From Fig. 15.29(b) we see that at v_Y = 0.1 V_D_D = 0.18 V, Q_p will be operating in the saturation region and i_D will be

[latex]i_{D} (0.1 V _{DD}) = \frac{1}{2}μ_{p}C_{ox} \left(\frac{W}{L}\right)_{p} (V_{DD} - |V_{tp}|)^{2}[/latex]

[latex] = \frac{1}{2} × 75 × \frac{0.54}{0.18} (1.8 − 0.5)^{2}[/latex]

= 190.1 μA

At v_Y = 0.9 V_DD = 1.62 V, Q_p will be operating in the triode region; thus,

[latex]i_{D} (0.9 V _{DD}) = μ_{p}C_{ox} \left(\frac{W}{L}\right)_{p} \left[(V_{DD} - |V_{tp}|) (V_{DD} − 0.9 V_{DD}) - \frac{1}{2} (V_{DD} − 0.9 V_{DD})^{2} \right][/latex]

[latex]= 75 × \frac{0.54}{0.18} \left[(1.8 − 0.5)(1.8 − 1.62) − \frac{1}{2} (1.8 − 1.62)^{2}\right][/latex]

= 49 μA

Thus the average capacitor charging current is

[latex]I_{av} = \frac{1}{2} (190.1 + 49) = 119.6 μA[/latex]

The rise time t_r of v_Y can now be determined from

[latex]t_{r} = \frac{C Δ v_{Y} }{I_{av}}[/latex]

[latex]= \frac{C (0.9 V_{DD} - 0.1 V_{DD})}{I_{av}}[/latex]

Thus,

[latex]t_{r} = \frac{20 × 10^{−15} × 0.8 × 1.8}{119.6 × 10^{−6}} = 0.24 ns[/latex]

(b) When A = B = C = D = 1, all the NMOS transistors will be conducting during the evaluation phase. Replacing the five identical transistors with an equivalent device Q_eq with (W/L)_eq = [latex]\frac{1}{5}[/latex] [latex](W/L) = \frac{1}{5} × 1.5 = 0.3 [/latex] , we obtain the equivalent circuit for the capacitor discharge, shown in Fig. 15.29(c). At v_Y = V_DD, Q_eq will be operating in saturation; thus,

[latex]i_{D} (V_{DD}) = \frac{1}{2}(μ_{n}C_{ox}) \left(\frac{W}{L}\right)_{eq} (V_{DD} - V_{t})^{2}[/latex]

[latex] = \frac{1}{2} × 300 × 0.3 (1.8 − 0.5)^{2}[/latex]

= 76.1 μA

At v_Y = V_DD/2, Q_eq will be operating in the triode region, thus,

[latex]i_{D} (V_{DD} /2) = (μ_{n}C_{ox}) \left(\frac{W}{L}\right)_{eq} \left[(V_{DD} - V_{t}) \frac{V_{DD}}{2} - \frac{1}{2} \left(\frac{V_{DD}}{2}\right)^{2}\right] [/latex]

[latex]= 300 × 0.3 \left[(1.8 − 0.5) \left(\frac{1.8}{2}\right) - \frac{1}{2} \left(\frac{1.8}{2}\right)^{2}\right][/latex]

= 68.9 μA

Thus the average capacitor-discharge current is

[latex]I_{av} = \frac{76.1 + 68.9}{2} = 72.5 μA[/latex]

and t_PHL can be found from

[latex]t_{PHL} = \frac{C (V_{DD} - V_{DD}/2)}{I_{av}}[/latex]

[latex]= \frac{20 × 10^{−15} (1.8 − 0.9)}{72.5 × 10^{−6}}= 0.25 ns[/latex]

Question 15.4: Consider the four-input, dynamic logic NAND gate shown in Fi...

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