Consider the NMOS transistor switch in the circuits of Figs. 15.17 and 15.18 to be fabricated in a technology for which μnCox = 50 μA/V², μpCox = 20 μA/V², |Vt0| = 1 V, γ = 0.5 V^1/2, 2 φf = 0.6 V, and VDD = 5 V, where φf is a physical parameter. Let the transistor be of the minimum size for this

Question

Consider the NMOS transistor switch in the circuits of Figs. 15.17 and 15.18 to be fabricated in a technology for which μ_nC_ox = 50 μA/V², μ_pC_ox = 20 μA/V², |V_t0| = 1 V, γ = 0.5 [latex]V^{1/2}[/latex], 2 φ_f = 0.6 V, and V_DD = 5 V, where φ_f is a physical parameter. Let the transistor be of the minimum size for this technology, namely, 4 μm/2 μm, and assume that the total capacitance between the output node and ground is C = 50 fF.

(a) For the case with v_I high (Fig. 15.17), find V_OH.

(b) If the output feeds a CMOS inverter whose (W/L)_p = 2.5 (W/L)_n =10 μm/2 μm, find the static current of the inverter and its power dissipation when its input is at the value found in (a). Also find the inverter output voltage.

(c) Find t_PLH.

(d) For the case with v_I going low (Fig. 15.18), find t_PHL.

(e) Find t_P.

Accepted Answer

(a) Refer to Fig. 15.17. If V_OH is the value of v_O at which Q stops conducting,

V_DD − V_OH − V_t = 0

then,

V_OH = V_D_D − V_t

where V_t is the value of the threshold voltage at a source–body reverse bias equal to V_OH. Using Eq. (15.34), we have

[latex]V_{t} = V_{t0} + γ \left(\sqrt{v_{O} + 2 φ_{f}} - \sqrt{ 2 φ_{f}}\right)[/latex] (15.34)

[latex]V_{t} = V_{t0} + γ \left(\sqrt{V_{OH} + 2 φ_{f}} - \sqrt{ 2 φ_{f}}\right)[/latex]

[latex]= V_{t0} + γ \left(\sqrt{V_{DD} - V_{t} + 2 φ_{f}} - \sqrt{ 2 φ_{f}}\right)[/latex]

Substituting V_t0 = 1, γ = 0.5, V_DD = 5, and 2 φ_f = 0.6, we obtain a quadratic equation in V_t whose solution yields

V_t = 1.6 V

Thus,

V_OH = 3.4 V

Note that this represents a significant loss in signal amplitude.

(b) The load inverter will have an input signal of 3.4 V. Thus, its Q_P will conduct a current of

[latex]i_{DP} = \frac{1}{2}× 20 × \frac{10}{5} (5 − 3.4 − 1)^{2} = 18 μA[/latex]

where we have assumed Q_P to be operating in saturation, as we still expect v_O of the inverter to be close to 0 V. Thus, the static power dissipation of the inverter will be

P_D = V_D_Di_DP = 5 × 18 = 90 μW

The output voltage of the inverter can be found by noting that Q_N will be operating in the triode region. Equating its current to that of Q_P (i.e., 18 μA) enables us to determine the output voltage to be 0.08 V.

(c) To determine t_PLH , refer to Fig. 15.17. We need to find the current i_D at t = 0 (where v_O = 0, V_t = V_t0 = 1 V) and at t = t_PLH (where v_O = 2.5 V, V_t to be determined), as follows:

[latex]i_{D} (0) = \frac{1}{2} × 50 × \frac{4}{2} × (5 − 1)^{2} = 800 μA[/latex]

[latex]V_{t} (at v_{O} = 2.5 V) = 1 + 0.5 (\sqrt{2.5 + 0.6} - \sqrt{0.6}) = 1.49 V[/latex]

[latex]i_{D}(t_{PLH}) = \frac{1}{2} × 50 × \frac{4}{2} (5 − 2.5 − 1.49)^{2} = 50 μA[/latex]

We can now compute the average discharge current as

[latex]i_{D} |_{av} = \frac{800 + 50}{2} = 425 μA[/latex]

and t_PLH can be found as

[latex]t_{PLH} = \frac{C(V_{DD}/2)}{i_{D} |_{av}}[/latex]

[latex]= \frac{50 × 10^{−15} × 2.5}{425 × 10^{−6}}= 0.29 ns[/latex]

(d) Refer to the circuit in Fig. 15.18. Observe that, here, V_t remains constant at V_t0 = 1 V.At t = 0, Q will be operating in saturation, and the drain current will be

[latex]i_{D}(0) = \frac{1}{2} × 50 × \frac{4}{2} (5 − 1)^{2} = 800 μA[/latex]

At t = t_PHL, Q will be operating in the triode region, and thus

[latex]i_{D} (t_{PHL}) = 50 × \frac{4}{2} \left[(5 − 1) × 2.5 − \frac{1}{2} × 2.5^{2}\right][/latex]

= 688 μA

Thus, the average discharge current is given by

[latex]I_{D} |_{av} = \frac{1}{2} (800+688) = 744 μA[/latex]

and t_PHL can be determined as

[latex]t_{PHL} = \frac{50 × 10^{−15} × 2.5}{744 × 10^{−6}} = 0.17 ns[/latex]

(e) [latex]t_{P} = \frac{1}{2} (t_{PLH} + t_{PHL}) = \frac{1}{2} (0.29 + 0.17) = 0.23 ns[/latex]

Question 15.3: Consider the NMOS transistor switch in the circuits of Figs....

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