Question 16.8: Objective: Calculate the power dissipation in a CMOS inverte...

Microelectronics Circuit Analysis and Design

Objective: Calculate the power dissipation in a CMOS inverter.

Consider a CMOS inverter with a load capacitance of $C_{L} = 2 pF$ biased at $V_{DD} = 5 V$ . The inverter switches at a frequency of f = 100 kHz.

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From Equation (16.52), power dissipation in the CMOS inverter is

$P = f E_{T} = f C_{L} V^{2}_{DD}$ (16.52)

$P = f C_{L} V^{2}_{DD} = (10^{5})(2 × 10^{−12})(5)^{2} ⇒ 5 µW$
Comment: Previously determined values of static power dissipation in NMOS inverters were on the order of 500 µW; therefore, power dissipation in a CMOS inverter is substantially smaller. In addition, in most digital systems, only a small fraction of the logic gates change state during each clock cycle; consequently, the power dissipation in a CMOS digital system is substantially less than in an NMOS digital system of similar complexity.

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