60GHz common-gate CMOS LNA design For the 60GHz LNA in Figure 7.26(b), the power supply voltage is 0.6V. The noise parameters of the n-MOSFET in the common-source configuration are listed in the Table 7.5 as a function of frequency. Assume g^′meff = 1.1mS/μm, g^′oeff = 0.11mS/μm, C^′gs = 1fF/μm.

Question

60GHz common-gate CMOS LNA design

For the 60GHz LNA in Figure 7.26(b), the power supply voltage is 0.6V. The noise parameters of the n-MOSFET in the common-source configuration are listed in the Table 7.5 as a function of frequency. Assume [latex]g^′_{meff} = 1.1mS/\mu m, g^′_{oeff} = 0.11mS/\mu m, C^′_{gs} = 1fF/\mu m[/latex].

(a) Determine the size and bias current of the transistor such that the real part of the optimum noise impedance is equal to [latex]50\Omega[/latex]. The minimum noise figure and optimum noise impedance of a common-gate stage can be assumed to be identical to those of the common-source stage.

(b) Calculate [latex]L_S[/latex], the transistor gate width and the bias current such that input impedance is matched to [latex]50\Omega[/latex] for [latex]R_P = 110\Omega[/latex]. What is the power gain if the output resonates at 60GHz and the input is matched to [latex]50\Omega[/latex]? The real part of the input impedance in the common-gate stage can be approximated by [latex]R_{IN} =\frac{1}{g_{meff}}+\frac{R_P}{1+\frac{g_{meff}}{g_{oeff}}}[/latex]?

(c) If the measured MAG (maximum available power gain) of the transistor is 9dB at 60GHz, how large can the effective [latex]R_p[/latex] at the output node really be? Is a [latex]700\Omega[/latex] value realistic? What would the power gain and [latex]R_{IN}[/latex] be in the latter case?

Table 7.5 Noise parameters of a 90nm 20×1μm n-MOSFETs at 0.15mA/μm, [latex]f_T[/latex] = 120GHz.
F(GHz)	Rn (Ω)	[latex]R_{SOPT}[/latex] (Ω)	[latex]X_{SOPT}[/latex] (Ω)	[latex]X_{IN}[/latex] (Ω)	[latex]F_{MIN}[/latex]	[latex]NF_{MIN}[/latex] (dB)
5	130.6	275	1237	-979.6	1.05	0.2
30	46.7	79.5	206	-164	1.4	1.46
60	38.26	45	103.5	-83.5	1.75	2.43

Accepted Answer

(a) We can use the data in the table and the fact that [latex]R_{SOPT} = R^′_{SOPT}/W[/latex].

At 60GHz [latex]R_{SOPT}[/latex] for a [latex]20\mu m[/latex] device is [latex]45\Omega[/latex]. Hence a device with [latex]W = 20 imes 45/50 = 18\mu m[/latex] will have [latex]R_{SOPT} = 50\Omega[/latex].

[latex]I_{DS} = W imes 0.15 mA/\mu m = 2.7 mA[/latex].

(b) [latex]R_{IN} =\frac{1}{g^′_{meff}W}+\frac{R_p}{1+\frac{g_{mef f}}{g_{oef f}}}=\frac{1}{g^′_{meff}W}+10=50Ohm[/latex]

[latex]W = \left\{25mS ight\}/\left\{1.1mS/μm, ight\} = 22.7\mu m[/latex]. We pick [latex]W = 23\mu m[/latex] and [latex]I_{DS} = 3.45mA[/latex] and [latex]g_{meff} = 25.3mS[/latex].

[latex]C_{gs} = W imes C^′_{gs} = 23fF[/latex]. [latex]C_{sb} = W imes C^′_{sb} = 25.3fF[/latex].

[latex]L_S =\frac{1}{ω^2(C_{gs} + C_{sb})} = 150pH[/latex]

This device size corresponds to a noise matching impedance of [latex]40\Omega[/latex]. A compromise between noise and input impedance matching would be to select [latex]W = 20\mu m[/latex] and thus end up with a noise impedance of [latex]45\Omega[/latex] and an input impedance of [latex]55\Omega[/latex].

(c) [latex]G<= ¼ g^2_{meff} R_p R_{IN}[/latex] for [latex]R_P=700\Omega[/latex]; [latex]R_{IN} = 40 + 700/11 =103.63\Omega[/latex] . [latex]G=11.6=10.6dB[/latex]. This value is larger than the transistor MAG. That means that [latex]R_P[/latex], which includes the output resistance of the MOSFET and that of the drain inductor, cannot be as high as [latex]700\Omega[/latex].

Question 7.5: 60GHz common-gate CMOS LNA design For the 60GHz LNA in Figur...

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