(a) The measured RSOPT of a 3130nm2.5μm HBT (3 emitter stripes, each 130nm wide and 2.5μm long) is 466.6Ω at 6GHz and JOPT = 2mA/μm^2. Find the total emitter length of a SiGe HBT with 130nm emitter width such that its RSOPT=50Ω at 6GHz. Calculate the bias current knowing that the HBT is biased at

Question

(a) The measured [latex]R_{ ext {SOPT }}[/latex] of a [latex]3 imes 130 \mathrm{~nm} imes 2.5 \mu \mathrm{m}[/latex] HBT (3 emitter stripes, each 130 [latex]\mathrm{nm}[/latex] wide and [latex]2.5 \mu \mathrm{m}[/latex] long) is [latex]466.6 \Omega[/latex] at [latex]6 \mathrm{GHz}[/latex] and [latex]J_{O P T}=2 \mathrm{~mA} / \mu \mathrm{m}^{2}[/latex]. Find the total emitter length of a SiGe HBT with [latex]130 \mathrm{~nm}[/latex] emitter width such that its [latex]R_{S O P T}=50 \Omega[/latex] at [latex]6 \mathrm{GHz}[/latex].

Calculate the bias current knowing that the HBT is biased at the optimum noise figure current density.

(b) Find the total gate width of a [latex]90 \mathrm{~nm}[/latex] planar [latex]\mathrm{n}[/latex]-MOSFET such that its [latex]R_{S O P T}=50 \Omega[/latex] at [latex]6 \mathrm{GHz}[/latex] knowing that the optimum noise resistance of a [latex]20 \mu \mathrm{m}[/latex] wide device with [latex]2 \mu \mathrm{m}[/latex] fingers is [latex]275 \Omega[/latex] at [latex]5 \mathrm{GHz}[/latex] when biased at the optimum noise figure current density [latex]J_{O P T}=[/latex] [latex]0.15 \mathrm{~mA} / \mu \mathrm{m}[/latex]

Accepted Answer

(a) If, for an HBT with a total emitter length of [latex]3 imes 2.5 \mu \mathrm{m}=7.5 \mu \mathrm{m} R_{S O P T}[/latex] is [latex]466.6 \Omega[/latex], then we need an emitter length of [latex]466.6 / 50 imes 7.5=70 \mu \mathrm{m}[/latex] to satisfy the noise matching condition.

This could be realized with N=28 emitters stripes each [latex]2.5 \mu \mathrm{m}[/latex] long. More realistically, to minimize interconnect resistance and die area, we could have five transistors connected in parallel, each with [latex]2 imes 7 \mu \mathrm{m}[/latex] emitters, i.e. [latex]l_{E}=7 \mu \mathrm{m}[/latex] and N=10 emitter stripes. The corresponding bias current (at the optimum noise current density) becomes [latex]2 imes 0.13 imes 70=18 \mathrm{~mA}[/latex]. In an older technology, with lower [latex]f_{T}[/latex] of [latex]45 \mathrm{GHz}[/latex] and [latex]0.5 \mu \mathrm{m}[/latex] wide emitters, the optimum noise current was only about [latex]3 \mathrm{~mA}[/latex] [3]. This significant increase in device size and current is partly due to the narrower emitter and partly due to the larger [latex]f_{T}[/latex] of new generation HBTs.

(b) Using a [latex]2 \mu \mathrm{m}[/latex] finger width contacted on one side, and taking advantage of the frequency dependence of the optimum source resistance, we obtain a total gate width [latex]W_{O P T}[/latex] of

[latex]W_{O P \mathrm{~T}}(6 \mathrm{GHz})=W(5 \mathrm{GHz}) imes \frac{5 \mathrm{GHz}}{6 \mathrm{GHZ}} imes \frac{R_{S O P T}(20 \mu \mathrm{m} @ 5 \mathrm{GHz})}{50 \Omega}=(20 \mu \mathrm{m}) imes \frac{5}{6} imes \frac{275}{50}=91.7 \mu \mathrm{m}[/latex]

The total gate width is rounded off to [latex]92 \mu \mathrm{m}[/latex] and corresponds to an optimal noise bias current of [latex]13.8 \mathrm{~mA}[/latex]
This completes the "active matching" part of the design. At this stage, the transistor is biased at the minimum noise figure current density, and exhibits the lowest possible minimum noise factor (figure) at that particular frequency. At the same time, the real part of its optimum noise impedance is equal to the real part of the signal source impedance, [latex]Z_{0}[/latex].

Question 7.1: (a) The measured RSOPT of a 3130nm2.5μm HBT (3 emitter strip...

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