6GHz and 12GHz LNA design in 180nm CMOS You have just been hired as an RF circuit designer by a fabless semiconductor company focusing on developing wireless products over a wide range of frequencies. Your boss has assigned you the task of designing a n-MOS cascode LNA (like the one in Figure

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6GHz and 12GHz LNA design in 180nm CMOS You have just been hired as an RF circuit designer by a fabless semiconductor company focusing on developing wireless products over a wide range of frequencies. Your boss has assigned you the task of designing a n-MOS cascode LNA (like the one in Figure [latex] 7.5(\mathrm{~d})[/latex] with a center frequency of [latex]6 \mathrm{GHz}[/latex] in a [latex]180 \mathrm{~nm}[/latex] RF CMOS process. While this may not be the most advanced technology, it has adequate performance for frequencies up to [latex]20 \mathrm{GHz}[/latex] and is very cost effective. At the same time, there is a pressing need to design a [latex]12 \mathrm{GHz} [/latex] LNA for a new satellite receiver, which also falls among your design responsibilities. You have the following data for the [latex]180 \mathrm{~nm}[/latex] RF CMOS process (Table 7.1).
[latex]C_{d b}^{\prime}, C_{s b}^{\prime}, C_{g s}^{\prime}, C_{g d}^{\prime}[/latex], and [latex]g_{m e f f}^{\prime}[/latex] represent the device capacitances and transcoductance per micron of gate width. Note that [latex]g_{m e f f}^{\prime} g_{o}^{\prime}, C_{g s}^{\prime}[/latex], and [latex]C_{d b}^{\prime}[/latex] already include the impact of [latex]R_{s}[/latex]. Assume that [latex]k_{1}=0.5[/latex]. Furthermore, assume that [latex]X_{S O P T}[/latex] is equal to [latex]1.15 \omega_{T} / \omega g_{m e f f}[/latex] and that the load inductor has a Q of 10 , irrespective of frequency and that the output of the LNA is terminated on a matched load.

Determine the transistor sizes and bias current, the required inductor values, and estimate the gain of the [latex]180 \mathrm{~nm}[/latex] CMOS cascode LNA.

Accepted Answer

Let us start with the [latex]6 \mathrm{GHz}[/latex] LNA. From device simulations, we find that, in this[latex]180 \mathrm{~nm}[/latex] process, the best finger width for minimum noise is [latex]W_{f}=2 \mu \mathrm{m}[/latex]. We can calculate [latex]g_{m}^{\prime}{ }_{m}=g_{m e f}^{\prime}\left(1-R_{s}^{\prime} \times\right. \left.g_{\text {meff }}^{\prime}\right)=0.434 \mathrm{mS} / \mu \mathrm{m}[/latex]. The first step is to size the transistors in the cascode such that [latex]R_{\text {SOPT }}[/latex]= 50Ω. At [latex]6 \mathrm{GHz}[/latex], we determine the gate width [latex]W_{G}=N_{f} \times W_{f}[/latex].

Table 7.1 180nm RF-CMOS process data.

180nm		Parameter
0.2mA / V2		[latex] k_{n}[/latex]
35GHz		[latex]f_{T} \text { (of n-MOS cascode stage) @ } 0.15 \mathrm{~mA} / \mu \mathrm{m} \[/latex]
1.1fF/μm		[latex]C_{d b / s b}^{\prime}\[/latex]
1.0fF/μm		[latex]C_{g s}^{\prime} \[/latex]
0.4fF/μm		[latex]C_{g d}^{\prime} \[/latex]
0.30dB		[latex]N F_{M I N} @ 6 \mathrm{GHz}, J_{O P T} \[/latex]
0.58dB		[latex]N F_{M I N} @ 12 \mathrm{GHz}, J_{O P T} \[/latex]
0.4mS/μm		[latex]g_{m e f f}^{\prime} @ 0.15 \mathrm{~mA} / \mu \mathrm{m} \[/latex]
0.04mS/μm		[latex]g_{o}^{\prime} @ 0.15 \mathrm{~mA} / \mu \mathrm{m} \[/latex]
200Ω×μm		[latex]R_{s}^{\prime} \[/latex]
2μm		[latex]W_{f}[/latex]
75Ω		[latex]R_{g}^{\prime}\left(W_{f}=2 \mu \mathrm{m}\right) \[/latex]
0.5V		[latex]V_{T}[/latex]
1.8V		[latex]V_{D D}[/latex]

[latex]\begin{aligned} N_{f} &=\frac{f_{T e f f}}{f Z_{0} W_{f} g_{m e f f}^{\prime}} \sqrt{\frac{g_{m}^{\prime} R_{s}^{\prime}+W_{f} g_{m}^{\prime} R_{g}^{\prime}\left(W_{f}\right)}{k_{1}}}=\ &=\frac{35}{6 \times 50 \times 2 \times 0.4 \times 10^{-3}} \sqrt{\frac{0.43 \times 0.2+2 \times 0.43 \times 10^{-3} \times 75}{0.5}} \approx 71 . \end{aligned}[/latex]
[latex]W=N_{f} \times W_{f}=142 \mu \mathrm{m}[/latex]. If we bias at [latex]J_{O P T}[/latex], the drain current is now fixed.

[latex]I_{D S}=J_{O P T} W=0.15 \frac{\mathrm{mA}}{\mu \mathrm{m}} \times 142 \mu \mathrm{m}=21.3 \mathrm{~mA} \text { and } \mathrm{g}_{\mathrm{meff}}=0.4 \mathrm{mS} 142=56.8 \mathrm{mS}[/latex] .
Fixing the gate width also sets the input capacitance, which can be used to determine the gat inductance needed to cancel out the imaginary part of the input impedance
[latex]L_{G}+L_{S}=\frac{\omega_{T}}{(2 \pi f)^{2} W g_{m e f f}^{\prime}}=\frac{6.28 \times 35 \times 10^{9}}{\left(6.28 \times 6 \times 10^{9}\right)^{2} \times 142 \mu \mathrm{m} \times 0.4 \frac{\mathrm{mS}}{\mu \mathrm{m}}}=2.72 \mathrm{nH}[/latex] .
Additionally, the degeneration inductance is a function of the cascode [latex]f_{T}[/latex]. The inductanc required to achieve a [latex]50 \Omega[/latex] input impedance match in the [latex]180 \mathrm{~nm}[/latex] design is calculated as

[latex]L_{S}=\frac{Z_{0}-R_{g}-R_{s}}{2 \pi f_{T}}=\frac{50-75 / 77-100 / 77}{6.28 \times 35 \times 10^{9}}=217 \mathrm{pH}[/latex]
which leaves [latex]L_{G}=2.72 \mathrm{nH}-217 \mathrm{pH}=2.5 \mathrm{nH}[/latex].
One option for the output network is to select the output inductor, [latex]L_{D}[/latex], such that it resonates with the transistor output capacitance at [latex]6 \mathrm{GHz}[/latex]. This output capacitance can be calculated as a function of the device size.
[latex]C_{O U T}=\left(C_{d b}^{\prime}+C_{g d}^{\prime}\right) W=(1.1+0.4) \frac{\mathrm{fF}}{\mu \mathrm{m}} \times 142 \mu \mathrm{m}=213 \mathrm{fF}[/latex]
At [latex]6 \mathrm{GHz}[/latex], the load inductor becomes
[latex]L_{D}=\frac{1}{(2 \pi \mathrm{f})^{2} \mathrm{C}_{\text {OUT }}}=\frac{1}{\left(6.28 \times 6 \times 10^{9}\right)^{2} \times 213 \mathrm{fF}}=3.3 \mathrm{nH}[/latex] .
If Q=10, then the equivalent parallel loss resistance of the inductor becomes
[latex]R_{P L}=2 \pi f_{0} Q L_{D}=6.28 \times 6 \times 10^{9} \times 10 \times 3.3 \times 10^{-9}=1244 \Omega[/latex] .
However, we must also consider the loading due to the output resistance of the cascode stage itself, [latex]r_{o u t}[/latex], which is approximated by [latex]g_{m} / g_{o}^{2}=1760 \Omega[/latex] for a [latex]180 \mathrm{~nm}[/latex] MOSFET cascode with a transconductance of [latex]56.8 \mathrm{mS}[/latex]. The output impedance then becomes [latex]R_{P L} / / r_{\text {out }}=728 \Omega[/latex]. The resulting maximum power gain is
[latex]|G|=\frac{f_{T}^{2}}{f_{0}^{2}} \frac{R_{p}}{4 Z_{0}}=\frac{5.833^{2} \times 728}{200}=126=21 \mathrm{~dB}[/latex] .
We can apply the same methodology to scale the design to [latex]12 \mathrm{GHz}[/latex]. As the frequency has doubled, the gate width required for noise matching is half that of the [latex]6 \mathrm{GHz}[/latex] design, or [latex]71 \mu \mathrm{m}[/latex]. Since the unit finger width is [latex]2 \mu \mathrm{m}[/latex], we will round the total gate width up to [latex]72 \mu \mathrm{m}[/latex] and 36 fingers. It follows that the current consumption, transconductance, and capacitances will also scale by a factor of 2

[latex]I_{D S}=J_{O P T} W=0.15 \frac{\mathrm{mA}}{\mu \mathrm{m}} \times 72 \mu \mathrm{m}=10.8 \mathrm{~mA} \text { and } g_{\text {meff }}=0.4 \mathrm{mS} \times 72=28.8 \mathrm{mS}[/latex] .
The total inductance required to tune out the input capacitance is now
[latex]L_{G}+L_{S}=\frac{\omega_{T}}{(2 \pi f)^{2} W g_{\text {meff }}^{\prime}}=\frac{6.28 \times 35 \times 10^{9}}{\left(6.28 \times 12 \times 10^{9}\right)^{2} \times 72 \mu \mathrm{m} \times 0.4 \frac{\mathrm{mS}}{\mu \mathrm{m}}}=1.46 \mathrm{nH}[/latex]
nearly half the value in the [latex]6 \mathrm{GHz}[/latex] design. The degeneration inductance depends only on the cascode [latex]f_{T}[/latex], and hence should remain unchanged from the previous design [latex](217 \mathrm{pH})[/latex]. The input inductance for the [latex]12 \mathrm{GHz}[/latex] LNA becomes
[latex]L_{G}=1.46 \mathrm{nH}-217 \mathrm{pH}=1.24 \mathrm{nH}[/latex] .
Similarly, the output capacitance reduces in half and is now only [latex]108 \mathrm{fF}[/latex], resulting in a load inductance of

Table 7.2 6GHz and 12GHz LNA parameters.

Design parameter	6GHz LNA	12GHz LNA	Comment
Gate width (W)	142μm	72μm	[latex]R_{SPOT}[/latex] scales inversely with frequency
Bias current ( [latex]I_{DS}[/latex])	21.3mA	10.8mA	Current density remains unchanged
Max. power gain (G)	21dB	15.8dB	5.2dB reduction due to lower transistor gain
Degeneration ( [latex]L_{S}[/latex] )	217pH	217pH	Depends only on technology
Input inductance ([latex]L_{G}[/latex] )	2.5nH	1.24nH	Lower [latex]C_{IN}[/latex] , higher [latex]ω_{0}[/latex]
Load inductance ([latex]L_{D}[/latex])	3.3nH	1.63nH	Reduced by half

[latex]L_{D}=\frac{1}{(2 \pi f)^{2} C_{\text {OUT }}}=\frac{1}{\left(6.28 \times 12 \times 10^{9}\right)^{2} \times 108 \mathrm{fF}}=1.63 \mathrm{nH}[/latex]
which, not surprisingly, is half that of the [latex]6 \mathrm{GHz}[/latex] design. The equivalent output parallel resistance is unchanged, as the doubling of frequency and halving of load inductance cancel each other
[latex]R_{P}=\left(2 \pi f_{0}\right) Q L_{D}=(2 \pi \times 12 \mathrm{GHz}) \times 10 \times 1.63 \mathrm{nH}=1228 \Omega[/latex] .
Now, after accounting for the output resistance of the amplifier ([latex]3472 \Omega[/latex] ), the maximum power gain of the [latex]12 \mathrm{GHz}[/latex] LNA is calculated as
[latex]|G|=\frac{f_{T}^{2}}{f_{0}^{2}} \frac{R_{P}}{4 Z_{0}}=\frac{2.91^{2} \times 907}{200}=38.4=15.8 \mathrm{~dB}[/latex] .
This value is almost [latex]6 \mathrm{~dB}[/latex] lower than that of the [latex]6 \mathrm{GHz} \mathrm{LNA}[/latex] and reflects the decreasing available gain of the transistor at higher frequencies. The key parameters of the [latex]6 \mathrm{GHz}[/latex] and [latex]12 \mathrm{GHz}[/latex] designs are summarized in Table 7.2.

In the previous design examples, we have ignored the parasitic resistances of [latex]L_{G}[/latex] and [latex]L_{S}[/latex] since they are not known before the inductor values are found and the inductor layouts are designed. In practice, especially at frequencies below [latex]10 \mathrm{GHz}[/latex], because of the relatively large inductor values, the series resistances [latex]R_{L G}[/latex] and [latex]R_{L S}[/latex] are comparable or larger than [latex]R_{g}[/latex] and [latex]R_{s}[/latex]. This leads to design iterations and larger transistors sizes than originally calculated.

Indeed, [latex]6 \mathrm{GHz}[/latex] and [latex]12 \mathrm{GHz}[/latex] CMOS cascode LNAs based on these design results were fabricated in a [latex]180 \mathrm{~nm}[/latex] RF-CMOS process and using the generic schematic from Figure 7.8 [6]. In each case, the LNAs were optimized for best possible noise performance. The optimized transistor widths were [latex]160 \mu \mathrm{m}[/latex] and [latex]80 \mu \mathrm{m}[/latex] for the [latex]6 \mathrm{GHz}[/latex] and [latex]12 \mathrm{GHz}[/latex] designs, respectively. [latex]L_{G}[/latex] was [latex]2.32 \mathrm{nH}[/latex] for the [latex]6 \mathrm{GHz}[/latex] LNA, and [latex]1.1 \mathrm{nH}[/latex] for the [latex]12 \mathrm{GHz}[/latex] design. In both cases, [latex]L_{S}[/latex] was [latex]350 \mathrm{pH}[/latex]. Excepting [latex]L_{S}[/latex], these values are within 10 % of the hand analysis, verifying that simple design equations can be applied to CMOS LNA designs which can easily be scaled in frequency.

Question 7.2: 6GHz and 12GHz LNA design in 180nm CMOS You have just been h...

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