Design of Analog CMOS Integrated Circuits 2nd. Edition by Behzad Razavi | 9780072524932 | 0072524936 | Holooly

Analog and Digital Signals and Systems, Circuit Analysis

Design of Analog CMOS Integrated Circuits

259 SOLVED PROBLEMS

Question: 19.8

Differential pairs are often used as “current switches.” As shown in Fig. 19.69, the circuit routes its tail current to either of the outputs according to the large swings controlling the gates of M1 and M2. Explain what happens at node X during switching. If the tail currents of a large number of ...

Verified Answer:

Recall from Chapter 4 that for the differential pa...

Question: 19.7

In a 600-MHz, 2-V CMOS microprocessor containing 15 million transistors, the supply current varies by 25 A in approximately 5 ns [5]. If the processor provides 200 bond wires for ground and 200 for VDD, estimate the resulting supply bounce. ...

Verified Answer:

Assuming a total inductance of 5 nH for each bond ...

Question: 19.6

Calculate the capacitance of a metal 4 pad and a metal 4/metal 3 pad. Assume dimensions of 75 μm × 75 μm and use the capacitance data shown in Fig. 19.50. ...

Verified Answer:

For a metal 4 pad,

\begin{aligned} C_{t o ...

Question: 19.5

In the layout of Fig. 19.44, a 100-μm metal 4 line is connected to a sequence of vias and contacts to reach the gate of a transistor. Calculate the thermal noise contributed by the line and the contacts. ...

Verified Answer:

Assuming

R_{\square } = 40 mΩ/\square[/late...

Question: 19.4

The circuit of Fig. 19.37(a) is designed for a nominal gain of C1/C2 = 8. How should C1 and C2 be laid out to ensure precise definition of the gain? ...

Verified Answer:

We form

C_1

as 8 unit capacitors,...

Question: 19.3

An A/D converter incorporates a resistor ladder consisting of 128 units made of n-well to generate equally-spaced reference voltages (Fig. 19.33). If the two ends of the ladder are connected to V1 = +1 V and V2 = +2 V, calculate the ratio R128/R1. ...

Verified Answer:

The width of the depletion region inside the n-wel...

Question: 19.2

Consider the bandgap circuit shown in Fig. 19.27. Choose the values of n, R1, and R2 such that Vout exhibits a zero temperature coefficient and the layout can be designed for high precision. ...

Verified Answer:

Since

V_{\text {out }}=V_{B E 3}+V_T\left(R...

Question: 19.1

A 5-μm/40-nm MOSFET biased at 1 mA exhibits a transconductance of 1/(100 Ω). If the sheet resistance of the gate polysilicon is equal to 30 Ω/, what is the widest finger that the structure can incorporate while ensuring that the gate thermal noise voltage is one-fifth of the gate-referred channel ...

Verified Answer:

If the transistor is laid out as N parallel finger...

Question: 18.3

A D/A converter incorporates N equal current sources implemented as NMOS devices, each having an aspect ratio of W/L [Fig. 18.23(a)]. Assuming that the interconnect between every two consecutive current sources has a small resistance, r, estimate the mismatch between IN and I1 ...

Verified Answer:

If r is sufficiently small, the circuit can be mod...

Question: 18.2

An amplifier with an input capacitance of Cin is to be ac-coupled to a preceding stage having an output resistance Rout . Considering both of the topologies depicted in Fig. 18.22 and allowing a maximum signal attenuation of 20%, determine the minimum value of the coupling capacitor and the ...

Verified Answer:

In Fig. 18.22(a), the attenuation is given by [lat...

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