Question 14.7: Determining the Effective Load Capacitance C and the Propaga...
Determining the Effective Load Capacitance C and the Propagation Delay
Consider a CMOS inverter fabricated in a 0.25-μm process for which Cox = 6 fF/μm², μnCox = 110 μA/V², μpCox = 30 μA/V², Vtn = –Vtp = 0.5 V, and VDD = 2.5 V. The W/L ratio of QN is 0.375 μm/0.25 μm, and that for QP is 1.125 μm/0.25 μm. The gate–source and gate–drain overlap capacitances are specified to be 0.3 fF/μm of gate width. Further, the effective (large-signal) values of drain–body capacitances are Cdbn = 1 fF and Cdbp = 1 fF. The wiring capacitance Cw = 0.2 fF. Find tPHL, tPLH , and tP when the inverter is driving an identical inverter.
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First, we determine the value of the equivalent capacitance C using Eqs. (14.58) and (14.59),
Cg3 + Cg4 = (WL)3Cox + (WL)4Cox + Cgsov3 + Cgdov3 + Cgsov4 + Cgdov4 (14.58)
C = 2 Cgd1 + 2 Cgd2 +Cdb1 + Cdb2 + Cg3 + Cg4 + Cw (14.59)
where
Cgd1 = 0.3 × Wn = 0.3 × 0.375 = 0.1125 fF
Cgd2 = 0.3 × Wp = 0.3 × 1.125 = 0.3375 fF
Cdb1 = 1 fF
Cdb2 = 1 fF
Cg3 = 0.375 × 0.25 × 6 + 2 × 0.3 × 0.375 = 0.7875 fF
Cg4 = 1.125 × 0.25 × 6 + 2 × 0.3 × 1.125 = 2.3625 fF
Cw = 0.2 fF
Thus,
C = 2 × 0.1125 + 2 × 0.3375 + 1 + 1 + 0.7875 + 2.3625 + 0.2 = 6.25 fF
Next we use Eqs. (14.51) and (14.52) to determine tPHL,
αn=2/[47 – VDD3Vtn+(VDDVtn)2] (14.51)
tPHL=kp′(W/L)pVDDαp (14.52)
αn=47 – 2.53 × 0.5 + (2.50.5)22=1.7
tPHL=110 × 10−6 ×(0.375/0.25) × 2.51.7 × 6.25 × 10−15=25.8 ps
Similarly, we use Eqs. (14.53) and (14.54) to determine tPHL ,
αp=2/[47 – VDD3∣Vtp∣+∣∣∣∣VDDVtp∣∣∣∣2] (14.53)
tPHL = 0.69 RNC (14.54)
αp = 1.7
tPLH=30 × 10−6 ×(1.125/0.25) × 2.51.7 × 6.25 × 10−15=31.5 ps
Finally, we determine tP as
tP=21(25.8+31.5) =28.7 ps