For the simple MOS inverter in Fig. 14.12(a): (a) Derive expressions for VOH, VOL, VIL , VIH , and VM. For simplicity, neglect channel-length modulation (i.e., assume λ = 0). Show that these inverter parameters can be expressed in terms of VDD, Vt , and (knRD). The latter parameter has the

Question

For the simple MOS inverter in Fig. 14.12(a):

(a) Derive expressions for V_OH, V_OL, V_IL , V_IH , and V_M. For simplicity, neglect channel-length modulation (i.e., assume λ = 0). Show that these inverter parameters can be expressed in terms of V_DD, V_t , and (k_nR_D). The latter parameter has the dimension of V^-1, and to simplify the expressions, denote k_nR_D ≡ 1/V_x .

(b) Show that V_x can be used as a design parameter for the inverter circuit. In particular, find the value of V_x that results in V_M = V_DD/2.

(c) Find numerical values for all parameters and for the inverter noise margins for V_DD = 1.8 V, V_t = 0.5 V, and V_x set to the value found in (b).

(d) For [latex]k_{n}^{′}[/latex] = 300 μA/V² and W/L = 1.5, find the required value of R_D and use it to determine the average power dissipated in the inverter, assuming that the inverter spends half of the time in each of its two states.

(e) Comment on the characteristics of this inverter circuit vis-à-vis the ideal characteristics as well as on its suitability for implementation in integrated-circuit form.

Accepted Answer

(a) Refer to Fig. 14.20. For v_I < V_t , the MOSFET is off, i_D = 0, and v_O = V_DD. Thus

V_OH = V_D_D (14.10)

As v_I exceeds V_t , the MOSFET turns on and operates initially in the saturation region. Assuming λ = 0,

[latex]i_{D} = \frac{1}{2} k_{n} (v_{I} - V_{t})^{2}[/latex]

and

[latex]v_{O} = V_{DD} - R_{D}i_{D} = V_{DD} - \frac{1}{2} k_{n} R_{D} (v_{I} - V_{t})^{2}[/latex]

substituting k_nR_D = 1/V_x , the BC segment of the VTC is described by

[latex]v_{O} = V_{DD} - \frac{1}{2 V_{x}}(v_{I} - V_{t})^{2}[/latex] (14.11)

To determine V_IL , we differentiate Eq. (14.11) and set dv_O/dv_I= −1,

[latex]\frac{dv_{O}}{dv_{t}} = - \frac{1}{V_{x}} (v_{I} - V_{t})[/latex]

[latex]-1 = - \frac{1}{V_{x}} (v_{IL} - V_{t})[/latex]

which results in

V_IL = V_t + V_x (14.12)

To determine the coordinates of the midpoint M, we substitute v_O= v_I = V_M in Eq. (14.11), thus obtaining

[latex]V_{DD} - V_{M} = \frac{1}{2 V_{x}} (V_{M} - V_{t})^{2}[/latex] (14.13)

which can be solved to obtain

[latex]V_{M} = V_{t} + \sqrt{2 (V_{DD} - V_{t}) V_{x} + V_{x}^{2}} - V_{x} [/latex] (14.14)

The boundary of the saturation-region segment BC, point C, is determined by substituting v_O= v_I − V_t in Eq. (14.11) and solving for v_O to obtain

[latex]V_{OC} = \sqrt{2 V_{DD} V_{x} + V_{x}^{2}} - V_{x}[/latex] (14.15)

and

[latex]V_{IC} = V_{t} \sqrt{2 V_{DD} V_{x} + V_{x}^{2}} - V_{x}[/latex] (14.16)

Beyond point C, the transistor operates in the triode region, thus

[latex]i_{D} = k_{n} \left[(v_{I} - V_{t}) v_{O} - \frac{1}{2} v_{O}^{2}\right] [/latex]

and the output voltage is obtained as

[latex]v_{O} = V_{DD} - \frac{1}{V_{x}}\left[(v_{I} - V_{t}) v_{O} - \frac{1}{2} v_{O}^{2}\right][/latex] (14.17)

which describes the segment CD of the VTC. To determine V_IH , we differentiate Eq. (14.17) and set dv_O/dv_I = −1:

[latex]\frac{dv_{O}}{dv_{I}} = - \left(\frac{1}{V_{x}}\right) \left[(v_{I} - V_{t}) \frac{dv_{O}}{dv_{I}} + v_{O} - v_{O} \frac{dv_{O}}{dv_{I}}\right][/latex]

[latex]-1 = -\frac{1}{V_{x}} \left[-(v_{IH} - V_{t}) +2 v_{O} \right][/latex]

which results in

V_IH − V_t = 2 v_O − V_x (14.18)

Substituting in Eq. (14.17) for v_I with the value of V_IH from Eq. (14.18) results in an equation in the value of v_O corresponding to v_I = V_IH, which can be solved to yield

[latex]v_{O} |_{v_{I} = V_{IH}} = 0.836 \sqrt{V_{DD} V_{x}} [/latex] (14.19)

which can be substituted in Eq. (14.18) to obtain

[latex]V_{IH} = V_{t} + 1.63 \sqrt{V_{DD} V_{x}} - V_{x}[/latex] (14.20)

To determine V_OL we substitute v_I = V_OH = V_DD in Eq. (14.17):

[latex]V_{OL} = V_{DD} - \frac{1}{V_{x}} \left[(V_{DD} - V_{t})V_{OL} - \frac{1}{2} V_{OL}^{2}\right][/latex] (14.21)

Since we expect V_OL to be much smaller than 2 (V_DD − V_t), we can approximate Eq. (14.21) as

[latex]V_{OL} \simeq V_{DD} - \frac{1}{V_{x}}(V_{DD} - V_{t})V_{OL}[/latex]

which results in

[latex]V_{OL} = \frac{V_{DD}}{1 + [(V_{DD} - V_{t})/V_{x}]}[/latex] (14.22)

It is interesting to note that the value of V_OL can alternatively be found by noting that at point D, the MOSFET switch has a closure resistance r_DS,

[latex] r_{DS} = \frac{1}{k_{n} (V_{DD} - V_{t})}[/latex] (14.23)

and V_OL can be obtained from the voltage divider formed by R_D and r_DS,

[latex]V_{OL} = V_{DD} \frac{r_{DS}}{R_{D} + r_{DS}} = \frac{V_{DD}}{1 + R_{D} / r_{DS}}[/latex] (14.24)

Substituting for r_DS from Eq. (14.23) gives an expression for V_OL identical to that in Eq. (14.22).

(b) We observe that all the inverter parameters derived above are functions of V_D_D, V_t , and V_x only. Since V_D_D and V_t are determined by the process technology, the only design parameter available is V_x ≡ 1/k_nR_D. To place V_M at half the supply voltage V_D_D, we substitute V_M= V_D_D/2 in Eq. (14.13) to obtain the value V_x must have as

[latex]V_{x}|_{V_{M} = V_{DD} / 2} = \frac{(V_{DD} / 2 - V_{t})^{2}}{V_{DD}}[/latex] (14.25)

(c) For V_D_D = 1.8 V and V_t = 0.5, we use Eq. (14.25) to obtain

[latex]V_{x}|_{V_{M} = 0.9 V} = \frac{(1.8 / 2 - 0.5)^{2}}{1.8} = 0.089 V[/latex]

From Eq. (14.10): V_OH = 1.8 V

From Eq. (14.22): V_OL = 0.12 V

From Eq. (14.12): V_IL = 0.59 V

From Eq. (14.20): V_IH = 1.06 V

NM_L = V_IL − V_OL = 0.47 V

NM_H= V_OH − V_IH = 0.74 V

(d) To determine R_D, we use

[latex]k_{n}R_{D} = \frac{1}{V_{x}} = \frac{1}{0.089} = 11.24[/latex]

Thus,

[latex]R_{D} = \frac{11.24}{k_{n}^{′} (W/L)} = \frac{11.24}{300 × 10^{−6} × 1.5} = 25 kΩ[/latex]

The inverter dissipates power only when the output is low, in which case the current drawn from the supply is

[latex]I_{DD} = \frac{V_{DD} - V_{OL}}{R_{D}} = \frac{1.8 - 0.12}{25 kΩ} = 67 μA[/latex]

and the power drawn from the supply during the low-output interval is

P_D = V_D_DI_D_D = 1.8 × 67 = 121 μW

Since the inverter spends half of the time in this state,

[latex]P_{Daverage} = \frac{1}{2} P_{D} = 60.5 μW[/latex]

(e) We now can make a few comments on the characteristics of this inverter circuit in comparison to the ideal characteristics:

1. The output signal swing, though not equal to the full power supply, is reasonably good: V_OH = 1.8 V, V_OL = 0.12 V.

2. The noise margins, though of reasonable values, are far from the optimum value of V_D_D/2. This is particularly the case for NM_L.

3. Most seriously, the gate dissipates a relatively large amount of power. To appreciate this point, consider an IC chip with a million inverters (a small number by today’s standards): Its power dissipation will be 61 W. This is too large, especially given that this is “static power,” unrelated to the switching activity of the gates (more on this later).

We consider this inverter implementation to be entirely unsuitable for IC fabrication because each inverter requires a load resistance of 25 kΩ, a value that needs a large chip area (see Appendix A). To overcome this problem, we investigate in Example 14.3 the replacement of the passive resistance R_D with a PMOS transistor.

Question 14.2: For the simple MOS inverter in Fig. 14.12(a): (a) Derive exp...

Related Answered Questions

Verified Answer:

Verified Answer:

Design of an Inverter Chain to Drive a Large Load Capacitance An inverter whose input capacitance C = 10 fF and whose equivalent output resistance R = 1 kΩ must ultimately drive a load capacitance CL = 1 pF. (a) What is the time delay ...

Verified Answer:

Transistor Sizing of a CMOS Gate Provide transistor W/L ratios for the logic circuit shown in Fig. 14.36. Assume that for the basic inverter n = 1.5 and p = 5 and that the channel length is 0.25 μm. ...

Verified Answer:

Determining the Effective Load Capacitance C and the Propagation Delay Consider a CMOS inverter fabricated in a 0.25-μm process for which Cox = 6 fF/μm², μnCox = 110 μA/V², ...

Verified Answer:

Verified Answer:

To eliminate the problem associated with the need for a large resistance RD in the circuit of Fig. 14.20(a), studied in Example 14.2, RD can be replaced by a MOSFET. One such possibility is the circuit in Fig. 14.21, where the load is a PMOS transistor QP whose gate is tied to ground in order to ...

Verified Answer:

Synthesize a CMOS logic circuit that implements the Boolean function Y = A + B (C + D) ...

Verified Answer: