Question 14.9: Design of an Inverter Chain to Drive a Large Load Capacitanc...

Microelectronic Circuits

Design of an Inverter Chain to Drive a Large Load Capacitance

An inverter whose input capacitance C = 10 fF and whose equivalent output resistance R = 1 kΩ must ultimately drive a load capacitance C_L = 1 pF.

(a) What is the time delay that results if the inverter is connected directly to C_L?

(b) If a driver chain such as that in Fig. 14.37(c) is used, how many inverters n and what size ratio x should you use to minimize the total delay? What is the total path delay achieved?

Figure 14.37

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