Consider a CMOS inverter fabricated in a 0.18-μm process for which VDD = 1.8 V, Vtn = |Vtp| = 0.5 V, μn = 4μp, and μnCox = 300 μA/V². In addition, QN and QP have L = 0.18 μm and (W/L)n = 1.5. (a) Find Wp that results in VM = VDD/2 = 0.9 V. What is the silicon area utilized by the inverter in this

Question

Consider a CMOS inverter fabricated in a 0.18-μm process for which V_DD = 1.8 V, V_tn = |V_tp| = 0.5 V, μ_n = 4μ_p, and μ_nC_ox = 300 μA/V². In addition, Q_N and Q_P have L = 0.18 μm and (W/L)_n = 1.5.

(a) Find W_p that results in V_M = V_DD/2 = 0.9 V. What is the silicon area utilized by the inverter in this case?

(b) For the matched case in (a), find the values of V_OH, V_OL, V_IH , V_IL , and the noise margins NM_L and NM_H. For v_I = V_IH , what value of v_O results? This can be considered the worst-case value of V_OL. Similarly, for v_I = V_IL , find v_O that is the worst-case value of V_OH. Now, use these worst-case values to determine more conservative values for the noise margins.

(c) For the matched case in (a), find the output resistance of the inverter in each of its two states.

(d) If λ_n = |λ_p| = 0.2 V^-1, what is the inverter gain at v_I = V_M? If a straight line is drawn through the point v_I = v_O = V_M with a slope equal to the gain, at what values of v_I does it intercept the horizontal lines v_O = 0 and v_O = V_DD? Use these intercepts to estimate the width of the transition region of the VTC.

(e) If W_p = W_n, what value of V_M results? What do you estimate the reduction of NM_L (relative to the matched case) to be? What is the percentage savings in silicon area (relative to the matched case)?

(f) Repeat (e) for the case W_p = 2 W_n. This case, which is frequently used in industry, can be considered to be a compromise between the minimum-area case in (e) and the matched case.

Accepted Answer

(a) To obtain V_M = V_DD/2 = 0.9 V, we select W_p according to Eq. (14.32),

[latex]\frac{W_{p}}{W_{n}} = \frac{μ_{n}}{μ_{p}} = 4[/latex]

Since W_n/L = 1.5, W_n = 1.5 × 0.18 = 0.27 μm. Thus,

W_p = 4 × 0.27 = 1.08 μm

For this design, the silicon area is

A = W_nL + W_pL = L (W_n + W_p)

= 0.18 (0.27 + 1.08) = 0.243 μm²

(b)

V_OH = V_DD = 1.8 V

V_OL = 0 V

To obtain V_IH we use Eq. (14.35),

[latex]V_{IH} = \frac{1}{8} (5 V_{DD} - 2 V_{t}) = \frac{1}{8} (5 × 1.8 - 2 × 0.5) = 1 V[/latex]

To obtain V_IL we use Eq. (14.36),

[latex]V_{IL} = \frac{1}{8} (3 V_{DD} + 2 V_{t}) = \frac{1}{8} (3 × 1.8 + 2 × 0.5) = 0.8 V[/latex]

We can now compute the noise margins as

NM_H = V_OH − V_IH = 1.8 − 1.0 = 0.8 V

NM_L = V_IL − V_OL = 0.8 − 0 = 0.8 V

As expected, NM_H = NM_L, and their value is very close to the optimum value of V_DD/2 = 0.9 V. For v_I = V_IH = 1 V, we can obtain the corresponding value of v_O by substituting in Eq. (14.34),

[latex]v_{O} = V_{IH} - \frac{V_{DD}}{2} = 1 - \frac{1.8}{2} = 0.1 V[/latex]

Thus, the worst-case value of V_OL, that is, V_OLmax, is 0.1 V, and the noise margin NM_L reduces to

NM_L = V_IL − V_OLmax = 0.8 − 0.1 = 0.7 V

From symmetry, we can obtain the value of v_O corresponding to v_I
= V_IL as

v_O = V_DD − 0.1 = 1.7 V

Thus the worst-case value of V_OH, that is, V_OHmin, is 1.7 V, and the noise margin NM_H reduces to

NM_H = V_OHmin − V_IH = 1.7 − 1 = 0.7 V

Note that the reduction in the noise margins is slight.

(c) The output resistance of the inverter in the low-output state is

[latex]r_{DSN} = \frac{1}{μ_{n}C_{ox} (W/L)_{n} (V_{DD} - V_{tn})}[/latex]

[latex]= \frac{1}{300 × 10^{−6} × 1.5 (1.8 − 0.5)} = 1.71 kΩ[/latex]

Since Q_N and Q_P are matched, the output resistance in the high-output state will be equal, that is,

r_DSP = r_DSN = 1.71 kΩ

(d) If the inverter is biased to operate at v_I = v_O = V_M = 0.9 V, then each of Q_N and Q_P will be operating at an overdrive voltage V_OV = V_M − V_t = 0.9 − 0.5 = 0.4 V and will be conducting equal dc currents I_D of

[latex]I_{D} = \frac{1}{2} μ_{n}C_{ox} \left(\frac{W}{L}\right)_{N} V_{OV}^{2}[/latex]

[latex]= \frac{1}{2} × 300 × 1.5 × 0.4^{2}[/latex]

= 36 μA

Thus, Q_N and Q_P will have equal transconductances:

[latex]g_{mn} = g_{mp} = \frac{2 I_{D}}{V_{OV}} = \frac{2 × 36}{0.4} = 0.18 mA/V^{2}[/latex]

Transistors Q_N and Q_P will have equal output resistances r_o,

[latex]r_{on} = r_{op} = \frac{|V_{A}|}{I_{D}} = \frac{1}{|λ| I_{D}} = \frac{1}{0.2 × 36} = 139 kΩ[/latex]

We can now compute the voltage gain at M as

A_v = − (g_mn + g_mp) (r_on || r_op)

= −(0.18 + 0.18) (139 || 139) = −25 V/V

When the straight line at M of slope −25 V/V is extrapolated, it intersects the line v_O = 0 at [0.9 + 0.9/25] = 0.936 V and the line v_O = V_DD at 0.9 − 0.9/25 = 0.864 V. Thus the width of the transition region can be considered to be (0.936 − 0.864) = 0.072 V.

(e) For W_p = W_n, the parameter r can be found from Eq. (14.40),

[latex]r = \sqrt{\frac{k_{p}}{k_{n}}} =\sqrt{\frac{μ_{p}W_{p}}{μ_{n}W_{n}}}[/latex] (14.40)

[latex]r = \sqrt{\frac{μ_{p}W_{p}}{μ_{n}W_{n}}} = \sqrt{\frac{1}{4} × 1} = 0.5[/latex]

The corresponding value of V_M can be determined from Eq. (14.39) as

[latex]V_{M} = \frac{r(V_{DD} - |V_{tp}|) + V_{tn}}{r + 1}[/latex] (14.39)

[latex]V_{M} = \frac{0.5 (1.8 − 0.5) + 0.5}{0.5 + 1} = 0.77 V[/latex]

Thus V_M shifts by only −0.13 V. Without recalculating V_IL we can estimate the reduction in NM_L to be approximately equal to the shift in V_M, that is, NM_L becomes 0.8 − 0.13 = 0.67 V. The silicon area for this design can be computed as follows:

A = L (W_n + W_p) = 0.18 (0.27 + 0.27)

= 0.0972 μm²

This represents a 60% reduction from the matched case!

(f) For W_p = 2 W_n,

[latex]r = \sqrt{\frac{1}{4} × 2} = \frac{1}{\sqrt{2}} = 0.707[/latex]

[latex]V_{M} = \frac{0.707 (1.8 − 0.5) + 0.5}{0.707 + 1} = 0.83 V[/latex]

Thus, relative to the matched case, the shift in V_M is only −0.07 V. We estimate that NM_L will decrease from 0.8 V by the same amount; thus NM_L becomes 0.73 V. In this case, the silicon area required is

A = L (W_n + W_p) = 0.18 (0.27 + 0.54)

= 0.146 μm²

which represents a 40% reduction relative to the matched case!

Question 14.4: Consider a CMOS inverter fabricated in a 0.18-μm process for...

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