# Question 7.4: Construct a MOD-10 counter with a four-bit binary MSI up cou......

Construct a MOD-10 counter with a four-bit binary MSI up counter.

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Both 74LS161 and 74LS163 are four-bit binary MSI up counters. The 74LS161 has an asynchronous reset input: if you use an asynchronous reset input to shorten the normal sequence and design a MOD-10 counter, an extra unstable state (count 10, 1010) is needed to help the counter return to zero. Whereas the 74LS163 has a synchronous reset input: if you use the synchronous reset input to design a MOD-10 counter, a clear signal is produced when the final state (count 9, 1001) is reached, but the counter will be reset at the next clock. Logic diagrams for MOD-10 counter constructed with a 74LS161 and a 74LS163 are shown in Figure 7.2.8. Tables 7.2.6 and 7.2.7 show the corresponding state table.
Another method to construct the MOD-10 counter is to use load input (  $\overline{_{LD}}$ ) to augment the capacity. When the load input  $\overline{_{LD}}$ is an active LOW, the data inputs are loaded to the outputs; thus, the counter sequence can be started from any four-bit binary number. Assume that ten states from 0110 to 1111 are used to construct the MOD-10 counter with 74LS161, as shown in Table 7.2.8. The initial state of the counter is set as 0110, and then the counter counts upward; after the tenth clock pulse, the output state is 1111 and the counter reaches the TC. Thus, the RCO is HIGH. The HIGH level emitted by the RCO is fed back to the load input via an inverter, so the load input $\overline{_{LD}}$ is a LOW, making the counter preset and recycle back to the initial state 0110.
Figure 7.2.9(a) shows the logic diagram for the MOD-10 counter with 74LS161 by selecting the count sequence from 0110 to 1111. Similarly, the first ten states from 0000 to 1001 can be used for implementing a MOD-10 counter with a 74LS161 and the corresponding logic diagram is shown in Figure 7.2.9(b).
In terms of the above two methods of augmenting the capacity of the counter, notice that whenever using the clear input, you should pay attention to the difference of synchronous clear and asynchronous clear. If using load input, you should pay attention to the initial state and end state of the design sequence, because initial state determines the connection of the data inputs and the end state gives the production method of load signal.

 Table 7.2.6: State sequence table. CP ${Q}_{3}$ ${Q}_{2}$ ${Q}_{1}$ ${Q}_{0}$ $\overline{R}$ 0 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 0
 Table 7.2.7: State sequence table. CP ${Q}_{3}$ ${Q}_{2}$ ${Q}_{1}$ ${Q}_{0}$ $\overline{R}$ 0 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 0
 Table 7.2.8: State sequence table. CP ${Q}_{3}$ ${Q}_{2}$ ${Q}_{1}$ ${Q}_{0}$ $\overline{R}$ 0 0 1 1 0 1 1 0 1 1 1 1 2 1 0 0 0 1 3 1 0 0 1 1 4 1 0 1 0 1 5 1 0 1 1 1 6 1 1 0 0 1 7 1 1 0 1 1 8 1 1 1 0 1 9 1 1 1 1 0

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