Question 7.1: Design a MOD-12 asynchronous counter with J–K flip-flops to ......

To design a MOD-12 asynchronous counter, four J–K flip-flops are required since they can afford any modulus less than or equal to 16 (2^{4}) . The counter counts up from 0000 to 1011, so when it goes to 1011, the next state should be 0000 to make the counter recycle back, as shown in Table 7.1.3.
Normally, the next state after 1011 is 1100, but now it must force the next state changing from 1011 to 0000. Figure 7.1.6 shows the MOD-12 counter, in which a NAND gate partially decodes count 1100 and resets all flip-flops. Thus, when the 12th clock pulse is coming, the counter is forced to recycle from 1011 to 0000.