Question 7.3: Design a three-bit synchronous binary up counter by using T ......
Design a three-bit synchronous binary up counter by using T flip-flops.
The first step to design a counter is to create a state diagram. A state diagram shows the transition of states through which the counter advances when it is clocked. Figure 7.2.2 shows a state diagram for a three-bit synchronous binary up counter.
The second step is to derive a state table, which lists all the present states, next states, and the inputs of T flip-flop as shown in Table 7.2.1. All possible output transitions are listed. Q and Q^{+} represent the present state and the next state.
The next step is to take use of the Karnaugh map to determine the excitation equation. Figure 7.2.3 shows the Karnaugh maps for the three flip-flops used in the counter.
From the Karnaugh maps, excitation equations of three flip-flops are
The last step is to construct the logic diagram, as shown in Figure 7.2.4.
| Table 7.2.1: State table. | ||||||||
| Present states | Next states | Inputs | ||||||
| {Q}_{2} | {Q}_{1} | {Q}_{0} | {Q_{2}}^{+} | {Q_{1}}^{+} | {Q_{0}}^{+} | {{T}}_{2} | {{T}}_{1} | {{T}}_{0} |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
