Question 14.7: Determining the Effective Load Capacitance C and the Propaga...
Determining the Effective Load Capacitance C and the Propagation Delay
Consider a CMOS inverter fabricated in a 0.25-μm process for which Cox = 6 fF/μm², μnCox = 110 μA/V², μpCox = 30 μA/V², Vtn = –Vtp = 0.5 V, and VDD = 2.5 V. The W/L ratio of QN is 0.375 μm/0.25 μm, and that for QP is 1.125 μm/0.25 μm. The gate–source and gate–drain overlap capacitances are specified to be 0.3 fF/μm of gate width. Further, the effective (large-signal) values of drain–body capacitances are Cdbn = 1 fF and Cdbp = 1 fF. The wiring capacitance Cw = 0.2 fF. Find tPHL, tPLH , and tP when the inverter is driving an identical inverter.
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