Question 15.2: Consider a pseudo-NMOS inverter fabricated in a 0.25-μm CMOS...
Consider a pseudo-NMOS inverter fabricated in a 0.25-μm CMOS technology for which μnCox = 115 μA/V², μpCox = 30 μA/V², Vtn = −Vtp = 0.5 V, and VDD = 2.5 V. Let the W/L ratio of QP be (0.25 μm/0.25 μm) and r = 9. Find:
(a) VOH, VOL, VIL, VIH , VM, NMH, and NML
(b) (W/L)n
(c) Istat and PD
(d) tPLH , tPHL, and tP, assuming a total capacitance at the inverter output of 7 fF
(a) VOH = VDD = 2.5 V
VOL is determined from Eq. (15.24) as
V_{OL} = (V_{DD} – V_{t}) \left[1 – \sqrt{1 – \frac{1}{r}} \right] (15.24)
V_{OL} = (2.5 – 0.5) \left[1 – \sqrt{1 – \frac{1}{9}} \right] = 0.11 V
VIL is determined from Eq. (15.20) as
V_{IL} = V_{t} + \frac{V_{DD} – V_{t}}{\sqrt{ r (r + 1})} (15.20)
V_{IL} = 0.5 + \frac{2.5 – 0.5}{\sqrt{9 (9 + 1)}} = 0.71 V
VIH is determined from Eq. (15.23) as
V_{IH} = V_{t} + \frac{2}{\sqrt{3 r}} (V_{DD} – V_{t}) (15.23)
V_{IH} = 0.5 + \frac{2}{\sqrt{3 × 9}} × (2.5 − 0.5) = 1.27 V
VM is determined from Eq. (15.21) as
V_{M} = V_{t} + \frac{V_{DD} – V_{t}}{\sqrt{r + 1}} (15.21)
V_{M} = 0.5 + \frac{2.5 – 0.5}{\sqrt{9 + 1}} = 1.13 V
The noise margins can now be determined as
NMH = VOH − VIH = 2.5 − 1.27 = 1.23 V
NML = VIL − VOL = 0.71 − 0.11 = 0.60 V
Observe that the noise margins are not equal and that NML is rather low.
(b) The W/L ratio of QN can be found from
\frac{μ_{n}C_{ox} (W/L)_{n}}{μ_{p}C_{ox}(W/L)_{p}} = 9
\frac{115 × (W/L)_{n}}{30 × 1} = 9
Thus,
(W/L)n = 2.35
(c) The dc current in the low-output state can be determined from Eq. (15.25) as
I_{stat} = \frac{1}{2} k_{p}(V_{DD} – V_{t})^{2} (15.25)
I_{stat} = \frac{1}{2} × 30 × 1 (2.5 − 0.5)^{2} = 60 μA
The static power dissipation can now be found from
PD = IstatVDD
= 60 × 2.5 = 150 μW
(d) The low-to-high propagation delay can be found by using Eqs. (15.28) and (15.29):
t_{PLH} \simeq \frac{α_{p}C}{k_{p}V_{DD}} (15.28)
α_{p} = 2 / \left[\frac{7}{4} – 3 \left(\frac{V_{t}}{V_{DD}}\right) + \left(\frac{V_{t}}{V_{DD}}\right)^{2} \right] (15.29)
αp = 1.68
t_{PLH} = \frac{1.68 × 7 × 10^{−15}}{30 × 10^{−6} × 1 × 2.5} = 0.16 ns
The high-to-low propagation delay can be found by using Eqs. (15.30) and (15.31):
t_{PHL} \simeq \frac{α_{n}C}{k_{n}V_{DD}} (15.30)
α_{n} = 2 / \left[1 + \frac{3}{4} \left(1 – \frac{1}{r}\right) – \left(3 – \frac{1}{r}\right) \left(\frac{V_{t}}{V_{DD}}\right) + \left(\frac{V_{t}}{V_{DD}}\right)^{2} \right] (15.31)
αn = 1.77
t_{PHL} = \frac{1.77 × 7 × 10^{−15}}{115 × 10^{−6} × 2.35 × 2.5} = 0.02 ns
Now, the propagation delay can be determined, as
t_{p} = \frac{1}{2} (0.16 + 0.02) = 0.09 ns
Although the propagation delay is considerably greater than that of a standard CMOS inverter, this is not an entirely fair comparison: Recall that the advantage of pseudo-NMOS occurs in gates with large fan-in, not in a single inverter.