Question 14.9: Design of an Inverter Chain to Drive a Large Load Capacitanc...
Design of an Inverter Chain to Drive a Large Load Capacitance
An inverter whose input capacitance C = 10 fF and whose equivalent output resistance R = 1 kΩ must ultimately drive a load capacitance CL = 1 pF.
(a) What is the time delay that results if the inverter is connected directly to CL?
(b) If a driver chain such as that in Fig. 14.37(c) is used, how many inverters n and what size ratio x should you use to minimize the total delay? What is the total path delay achieved?
(a) tP = τ = CLR = 10-12 × 103 = 1 ns.
(b) The delay is minimized by selecting
x = e = 2.718
and
x^{n} = \frac{C_{L}}{C} = \frac{10^{-12}}{10 × 10^{−15} } = 100
which yields
n =\frac{\ln 100}{\ln x} = \frac{\ln 100}{\ln e} = 4.6
Since we must use an integral number of inverters, we select
n = 5
and obtain x from
x^{n} = x^{5} = \frac{C_{L}}{C} = 100
which yields
x = (100)1/5 = 2.51
The total path delay will be
tP = nxCR
= 5 × 2.51 × 10 × 10-15 × 103 = 125.5 ps
which is a reduction in delay by a factor of about 8!