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Question 14.8: Transistor Sizing of a CMOS Gate Provide transistor W/L rati...

Transistor Sizing of a CMOS Gate

Provide transistor W/L ratios for the logic circuit shown in Fig. 14.36. Assume that for the basic inverter n = 1.5 and p = 5 and that the channel length is 0.25 μm.

Figure 14.36
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Refer to Fig. 14.36, and consider the PDN first. We note that the worst case occurs when QNB is on and either QNC or QND is on. That is, in the worst case, we have two transistors in series. Therefore, we select each of QNB, QNC, and QND to have twice the width of the n-channel device in the basic inverter, thus

QNB: W/L = 2n = 3 = 0.75/0.25

QNC: W/L = 2n = 3 = 0.75/0.25

QND: W/L = 2n = 3 = 0.75/0.25

For transistor QNA, select W/L to be equal to that of the n-channel device in the basic inverter:

QNA: W/L = n = 1.5 = 0.375/0.25

Next, consider the PUN. Here, we see that in the worst case, we have three transistors in series: QPA, QPC, and QPD. Therefore, we select the W/L ratio of each of these to be three times that of QP in the basic inverter, that is, 3p, thus

QPA: W/L = 3p = 15 = 3.75/0.25

QPC: W/L = 3p = 15 = 3.75/0.25

QPD: W/L = 3p = 15 = 3.75/0.25

Finally, the W/L ratio for QPB should be selected so that the equivalent W/L of the series connection of QPB and QPA should be equal to p. It follows that for QPB the ratio should be 1.5p,

QPB: W/L = 1.5p = 7.5 = 1.875/0.25

Figure 14.36 shows the circuit with the transistor sizes indicated.

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