Determine the gate material and design the semiconductor doping concentration to yield a specified threshold voltage.

Consider a MOS device with silicon dioxide and an n-type silicon substrate. The oxide thickness is $t_{0 x}=12 \mathrm{~nm}=120 \mathring{A}$ and the oxide charge is $Q_{s s}^{\prime}=2 \times 10^{10} \mathrm{~cm}^{-2}$ . The threshold voltage is to be approximately $V_{T P}=-0.3 \mathrm{~V}$ .

Question

Determine the gate material and design the semiconductor doping concentration to yield a specified threshold voltage.

Consider a MOS device with silicon dioxide and an n-type silicon substrate. The oxide thickness is [latex]t_{0 x}=12 \mathrm{~nm}=120 \mathring{A} [/latex] and the oxide charge is [latex]Q_{s s}^{\prime}=2 imes 10^{10} \mathrm{~cm}^{-2}[/latex]. The threshold voltage is to be approximately [latex]V_{T P}=-0.3 \mathrm{~V}[/latex].

Accepted Answer

The solution to this design problem is not straight forward, since the doping concentration parameter appears in the terms [latex]\phi_{f m}, x_{d T}, Q_{S D}^{\prime}[/latex] (max), and [latex]\phi_{m s}[/latex]. The threshold voltage, then, is a nonlinear function of [latex]N_{d}[/latex]. We resort to trial and error to obtain a solution.

Figure [latex]10.22[/latex] shows the threshold voltage for an aluminum gate system. Since the required threshold voltage in this problem is less negative than the values shown in Figure 10.22, we require a metal-semiconductor work function difference value that is more positive than for the aluminum gate. We therefore choose a [latex]\mathrm{p}^{+}[/latex]polysilicon gate.

Consider a doping concentration of [latex]N_{d}=10^{17} \mathrm{~cm}^{-3}[/latex]. From Figure [latex]10.16[/latex], the metalsemiconductor work function difference is [latex]\phi_{m s} \cong+1.1 \mathrm{~V}[/latex]. The remaining parameters are found to be

[latex] \begin{array}{l} \phi_{f n}=V_{t} \ln \left(\frac{N_{d}}{n_{i}} ight)=(0.0259) \ln \left(\frac{10^{17}}{1.5 imes 10^{10}} ight)=0.407 \mathrm{~V} \ x_{d T}=\left(\frac{4 \epsilon_{s} \phi_{f n}}{e N_{d}} ight)^{1 / 2}=\left\{\frac{4(11.7)\left(8.85 imes 10^{-14} ight)(0.407)}{\left(1.6 imes 10^{-19} ight)\left(10^{17} ight)} ight\}^{1 / 2} \ =1.026 imes 10^{-5} \mathrm{~cm} \ \begin{aligned} \left|Q_{S D}^{\prime}(\max ) ight| &=e N_{d} x_{d T}=\left(1.6 imes 10^{-19} ight)\left(10^{17} ight)\left(1.026 imes 10^{-5} ight) \ &=1.642 imes 10^{-7} \mathrm{C} / \mathrm{cm}^{2} \end{aligned} \end{array} [/latex]

The threshold voltage is determined to be

[latex] V_{T P}=\left[-\left|Q_{S D}^{\prime}(\max ) ight|-Q_{s s}^{\prime} ight] \cdot\left(\frac{t_{0 x}}{\epsilon_{0 x}} ight)+\phi_{m s}-2 \phi_{f n} [/latex]

or

[latex] \begin{array}{l} V_{T P}=\frac{\left[-\left(1.642 imes 10^{-7} ight)-\left(2 imes 10^{10} ight)\left(1.6 imes 10^{-19} ight) ight] \cdot\left(120 imes 10^{-8} ight)}{(3.9)\left(8.85 imes 10^{-14} ight)}\ +1.1-2(0.407) \end{array} [/latex]

which yields

[latex]V_{T P}=-0.296 \mathrm{~V} \cong-0.3 \mathrm{~V}[/latex]

Comment

The negative threshold voltage, with the [latex]\mathrm{n}[/latex]-type substrate, implies that this MOS capacitor is an enhancement mode device. The inversion layer charge is zero with zero applied gate voltage, and a negative gate voltage must be applied to induce the hole inversion charge.

Question 10.5: Determine the gate material and design the semiconductor dop...

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